drivers/gpu/drm/panel/panel-tpo-td043mtea1.c

108

td043mtea1_write(lcd, 0x11, val);

drivers/gpu/drm/panel/panel-tpo-td043mtea1.c

112

td043mtea1_write(lcd, 0x12, val);

drivers/gpu/drm/panel/panel-tpo-td043mtea1.c

116

td043mtea1_write(lcd, 0x13, val);

drivers/gpu/drm/panel/panel-tpo-td043mtea1.c

120

td043mtea1_write(lcd, 0x14 + i, gamma[i] & 0xff);

drivers/gpu/drm/panel/panel-tpo-td043mtea1.c

130

return td043mtea1_write(lcd, 4, reg4);

drivers/gpu/drm/panel/panel-tpo-td043mtea1.c

149

td043mtea1_write(lcd, 2, TPO_R02_MODE(lcd->mode) | TPO_R02_NCLK_RISING);

drivers/gpu/drm/panel/panel-tpo-td043mtea1.c

150

td043mtea1_write(lcd, 3, TPO_R03_VAL_NORMAL);

drivers/gpu/drm/panel/panel-tpo-td043mtea1.c

151

td043mtea1_write(lcd, 0x20, 0xf0);

drivers/gpu/drm/panel/panel-tpo-td043mtea1.c

152

td043mtea1_write(lcd, 0x21, 0xf0);

drivers/gpu/drm/panel/panel-tpo-td043mtea1.c

166

td043mtea1_write(lcd, 3, TPO_R03_VAL_STANDBY | TPO_R03_EN_PWM);

drivers/gpu/drm/panel/panel-tpo-td043mtea1.c

173

td043mtea1_write(lcd, 3, TPO_R03_VAL_STANDBY);

drivers/gpu/drm/panel/panel-tpo-td043mtea1.c

234

td043mtea1_write(lcd, 2, val);