tc_writel
tc_writel(0, &tr->Int_En);
tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl);
tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
tc_writel(dmactl | DMA_IntMask, &tr->DMA_Ctl);
tc_writel(status & ~(Int_BLEx | Int_FDAEx),
tc_writel(status & (Int_BLEx | Int_FDAEx),
tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl);
tc_writel(TX_THRESHOLD_MAX, &tr->TxThrsh);
tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
tc_writel(cam_index - 2, &tr->CAM_Adr);
tc_writel(cam_data, &tr->CAM_Data);
tc_writel(cam_index + 2, &tr->CAM_Adr);
tc_writel(cam_data, &tr->CAM_Data);
tc_writel(cam_index, &tr->CAM_Adr);
tc_writel(cam_data, &tr->CAM_Data);
tc_writel(cam_index + 4, &tr->CAM_Adr);
tc_writel(cam_data, &tr->CAM_Data);
tc_writel(saved_addr, &tr->CAM_Adr);
tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl);
tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl);
tc_writel(0, &tr->CAM_Ctl);
tc_writel(ena_bits, &tr->CAM_Ena);
tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
tc_writel(MAC_Reset, &tr->MAC_Ctl);
tc_writel(0, &tr->MAC_Ctl);
tc_writel(0, &tr->DMA_Ctl);
tc_writel(0, &tr->TxThrsh);
tc_writel(0, &tr->TxPollCtr);
tc_writel(0, &tr->RxFragSize);
tc_writel(0, &tr->Int_En);
tc_writel(0, &tr->FDA_Bas);
tc_writel(0, &tr->FDA_Lim);
tc_writel(0xffffffff, &tr->Int_Src); /* Write 1 to clear */
tc_writel(0, &tr->CAM_Ctl);
tc_writel(0, &tr->Tx_Ctl);
tc_writel(0, &tr->Rx_Ctl);
tc_writel(0, &tr->CAM_Ena);
tc_writel(DMA_TestMode, &tr->DMA_Ctl);
tc_writel(i, &tr->CAM_Adr);
tc_writel(0, &tr->CAM_Data);
tc_writel(0, &tr->DMA_Ctl);
tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
tc_writel(DMA_BURST_SIZE | DMA_RxAlign_2, &tr->DMA_Ctl);
tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl);
tc_writel(0, &tr->TxPollCtr); /* Batch mode */
tc_writel(TX_THRESHOLD, &tr->TxThrsh);
tc_writel(INT_EN_CMD, &tr->Int_En);
tc_writel(fd_virt_to_bus(lp, lp->rfd_base), &tr->FDA_Bas);
tc_writel((unsigned long)lp->rfd_limit - (unsigned long)lp->rfd_base,
tc_writel(fd_virt_to_bus(lp, lp->fbl_ptr), &tr->BLFrmPtr); /* start DMA receiver */
tc_writel(RX_CTL_CMD, &tr->Rx_Ctl); /* start MAC receiver */
tc_writel(txctl, &tr->Tx_Ctl);
tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA);
tc_writel(val, &tr->MD_Data);
tc_writel(MD_CA_Busy | MD_CA_Wr | (mii_id << 5) | (regnum & 0x1f),
tc_writel(reg, &tr->MAC_Ctl);
tc_writel(reg, &tr->MAC_Ctl);
tc_writel(reg, &tr->MAC_Ctl);
tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr,
tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl);