tc_readl
tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl);
dev->name, tc_readl(&tr->Tx_Stat));
u32 dmactl = tc_readl(&tr->DMA_Ctl);
(void)tc_readl(&tr->Int_Src); /* flush */
status = tc_readl(&tr->Int_Src);
status = tc_readl(&tr->Int_Src);
tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl);
dev->stats.rx_missed_errors += tc_readl(&tr->Miss_Cnt);
saved_addr = tc_readl(&tr->CAM_Adr);
cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000;
cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff;
while (tc_readl(&tr->MAC_Ctl) & MAC_Reset) {
(void)tc_readl(&tr->Miss_Cnt); /* Read to clear */
while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
return tc_readl(&tr->MD_Data) & 0xffff;
while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
reg = tc_readl(&tr->MAC_Ctl);
tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr,
while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
data = tc_readl(&tr->PROM_Data);