drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

107

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA,

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

109

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L0_CKSEL, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

110

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA,

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

112

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L1_CKSEL, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

113

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA,

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

115

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L2_CKSEL, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

122

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANAA8_CSIXA,

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

124

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANAA8_CSIXA,

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

126

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANAA8_CSIXA,

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

139

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA24_CSIXA, RG_CSIXA_RESERVE, 0x40);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

141

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_WRAPPER80_CSIXA, CSR_CSI_RST_MODE, 0);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

144

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, RG_CSIXA_BG_CORE_EN, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

147

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, RG_CSIXA_BG_LPF_EN, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

161

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, RG_CSIXA_BG_CORE_EN, 0);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

162

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, RG_CSIXA_BG_LPF_EN, 0);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

48

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, RG_CSI0A_L0_T0AB_EQ_IS, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

49

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, RG_CSI0A_L0_T0AB_EQ_BW, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

50

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA1C_CSIXA, RG_CSI0A_L1_T1AB_EQ_IS, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

51

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA1C_CSIXA, RG_CSI0A_L1_T1AB_EQ_BW, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

52

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA20_CSI0A, RG_CSI0A_L2_T1BC_EQ_IS, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

53

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA20_CSI0A, RG_CSI0A_L2_T1BC_EQ_BW, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

65

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L0_EQ_IS, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

66

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L0_EQ_BW, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

67

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L1_EQ_IS, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

68

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L1_EQ_BW, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

69

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA1C_CSIXA, RG_CSI1A_L2_EQ_IS, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

70

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA1C_CSIXA, RG_CSI1A_L2_EQ_BW, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

85

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA,