t4_write_reg
t4_write_reg(padap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
t4_write_reg(padap, qbase->reg_addr, func);
t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
t4_write_reg(padap, LE_DB_DBGI_REQ_DATA_A + (i << 2), 0);
t4_write_reg(padap, LE_DB_DBGI_REQ_TCAM_CMD_A, val);
t4_write_reg(padap, LE_DB_DBGI_CONFIG_A, val);
t4_write_reg(padap, ULP_TX_ASIC_DEBUG_CTRL_A, 0x1);
t4_write_reg(adap, MPS_TRC_CFG_A, TRC_RSS_ENABLE);
t4_write_reg(adap, MPS_TRC_CFG_A, TRC_RSS_DISABLE);
t4_write_reg(adap, MPS_T5_TRC_RSS_CONTROL_A, j);
t4_write_reg(adap, MPS_TRC_RSS_CONTROL_A, j);
t4_write_reg(adap,
t4_write_reg(adap,
t4_write_reg(adap,
t4_write_reg(adap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
t4_write_reg(adap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
t4_write_reg(adap, PM_RX_STAT_CONFIG_A, 0);
t4_write_reg(adap, PM_TX_STAT_CONFIG_A, 0);
t4_write_reg(adap, is_t4(adap->params.chip) ?
t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A, 0);
t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A, 0);
t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A,
t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A,
t4_write_reg(adap,
t4_write_reg(adap,
t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) |
t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
t4_write_reg(q->adap, MYPF_REG(SGE_PF_GTS_A),
t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
t4_write_reg(adap, MYPF_REG(PCIE_PF_CLI_A), 0);
t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
t4_write_reg(adap, TP_PACE_TABLE_A, 0xffff0000 + i);
t4_write_reg(adap, SGE_CTXT_CMD_A, CTXTQID_V(cid) | CTXTTYPE_V(ctype));
t4_write_reg(adap, addr_reg, start_idx);
t4_write_reg(adap, addr_reg, start_idx++);
t4_write_reg(adap, data_reg, *vals++);
t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
t4_write_reg(adapter, SF_DATA_A, val);
t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
t4_write_reg(adap, ctl_reg, 0);
t4_write_reg(adap, ctl_reg, 0);
t4_write_reg(adapter, reg, status);
t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
t4_write_reg(adapter, CIM_HOST_INT_CAUSE_A,
t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
t4_write_reg(adapter, addr, v);
t4_write_reg(adap, MA_INT_CAUSE_A, status);
t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
t4_write_reg(adapter, PL_INT_CAUSE_A, raw_cause & GLBL_INTR_MASK);
t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
t4_write_reg(adap,
t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
t4_write_reg(adap, TP_MTU_TABLE_A,
t4_write_reg(adap, TP_CCTRL_TABLE_A,
t4_write_reg(adap, TP_PIO_ADDR_A, addr);
t4_write_reg(adap, TP_PIO_DATA_A, val);
t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
t4_write_reg(adap, addr,
t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
t4_write_reg(adap, data_reg, tp->data[i]);
t4_write_reg(adap, mask_reg, ~tp->mask[i]);
t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
t4_write_reg(adap, mem_base + offset,
t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
t4_write_reg(adap,
t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */
t4_write_reg(adapter, DBG_GPIO_EN_A, 0);
t4_write_reg(adapter, a_port_cfg,
t4_write_reg(adapter, addr, v | val);
t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
t4_write_reg(rspq->adapter, T4VF_SGE_BASE_ADDR + SGE_VF_GTS,
t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_GTS,
t4_write_reg(rspq->adapter,
t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_GTS,
t4_write_reg(adapter,
t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_KDOORBELL,
t4_write_reg(adapter, mbox_ctl,
t4_write_reg(adapter, mbox_ctl,
t4_write_reg(adapter, mbox_ctl,