sst_dac_write
sst_dac_write(DACREG_ICS_PLLRMA, DACREG_ICS_PLL_CTRL);
sst_dac_write(DACREG_ICS_PLLWMA, 0x0); /* CLK0, f0 */
sst_dac_write(DACREG_ICS_PLLDATA, t->m);
sst_dac_write(DACREG_ICS_PLLDATA, t->p << 5 | t->n);
sst_dac_write(DACREG_ICS_PLLWMA, DACREG_ICS_PLL_CTRL);
sst_dac_write(DACREG_ICS_PLLDATA,
sst_dac_write(DACREG_ICS_PLLWMA, 0xa); /* CLK1, fA */
sst_dac_write(DACREG_ICS_PLLDATA, t->m);
sst_dac_write(DACREG_ICS_PLLDATA, t->p << 5 | t->n);
sst_dac_write(DACREG_ICS_PLLWMA, DACREG_ICS_PLL_CTRL);
sst_dac_write(DACREG_ICS_PLLDATA,
sst_dac_write(DACREG_WMA, 0); /* backdoor */
sst_dac_write(DACREG_WMA, 0); /* backdoor */
sst_dac_write(DACREG_RMR, (cr0 & 0x0f) | DACREG_CR0_16BPP);
sst_dac_write(DACREG_ICS_CMD, DACREG_ICS_CMD_16BPP);
sst_dac_write(DACREG_WMA, 0); /* backdoor */
sst_dac_write(DACREG_WMA, 0); /* backdoor */
sst_dac_write(DACREG_ICS_PLLRMA, 0x1); /* f1 */
sst_dac_write(DACREG_ICS_PLLRMA, 0x7); /* f7 */
sst_dac_write(DACREG_ICS_PLLRMA, 0xb); /* fB */
sst_dac_write(DACREG_WMA, 0); /* backdoor */
sst_dac_write(DACREG_WMA, 0);
sst_dac_write(DACREG_RMR, (cr0 & 0xf0)