sys_insn - Linux

arch/arm64/include/asm/sysreg.h

1045

#define GICV5_OP_GIC_CDAFF sys_insn(1, 0, 12, 1, 3)

arch/arm64/include/asm/sysreg.h

1046

#define GICV5_OP_GIC_CDDI sys_insn(1, 0, 12, 2, 0)

arch/arm64/include/asm/sysreg.h

1047

#define GICV5_OP_GIC_CDDIS sys_insn(1, 0, 12, 1, 0)

arch/arm64/include/asm/sysreg.h

1048

#define GICV5_OP_GIC_CDHM sys_insn(1, 0, 12, 2, 1)

arch/arm64/include/asm/sysreg.h

1049

#define GICV5_OP_GIC_CDEN sys_insn(1, 0, 12, 1, 1)

arch/arm64/include/asm/sysreg.h

1050

#define GICV5_OP_GIC_CDEOI sys_insn(1, 0, 12, 1, 7)

arch/arm64/include/asm/sysreg.h

1051

#define GICV5_OP_GIC_CDPEND sys_insn(1, 0, 12, 1, 4)

arch/arm64/include/asm/sysreg.h

1052

#define GICV5_OP_GIC_CDPRI sys_insn(1, 0, 12, 1, 2)

arch/arm64/include/asm/sysreg.h

1053

#define GICV5_OP_GIC_CDRCFG sys_insn(1, 0, 12, 1, 5)

arch/arm64/include/asm/sysreg.h

1054

#define GICV5_OP_GICR_CDIA sys_insn(1, 0, 12, 3, 0)

arch/arm64/include/asm/sysreg.h

119

sys_insn((op0), (op1), (CRn), (CRm), (op2)) | \

arch/arm64/include/asm/sysreg.h

127

#define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)

arch/arm64/include/asm/sysreg.h

128

#define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4)

arch/arm64/include/asm/sysreg.h

129

#define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6)

arch/arm64/include/asm/sysreg.h

130

#define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)

arch/arm64/include/asm/sysreg.h

131

#define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4)

arch/arm64/include/asm/sysreg.h

132

#define SYS_DC_CGDSW sys_insn(1, 0, 7, 10, 6)

arch/arm64/include/asm/sysreg.h

133

#define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)

arch/arm64/include/asm/sysreg.h

134

#define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4)

arch/arm64/include/asm/sysreg.h

135

#define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6)

arch/arm64/include/asm/sysreg.h

137

#define SYS_IC_IALLUIS sys_insn(1, 0, 7, 1, 0)

arch/arm64/include/asm/sysreg.h

138

#define SYS_IC_IALLU sys_insn(1, 0, 7, 5, 0)

arch/arm64/include/asm/sysreg.h

139

#define SYS_IC_IVAU sys_insn(1, 3, 7, 5, 1)

arch/arm64/include/asm/sysreg.h

141

#define SYS_DC_IVAC sys_insn(1, 0, 7, 6, 1)

arch/arm64/include/asm/sysreg.h

142

#define SYS_DC_IGVAC sys_insn(1, 0, 7, 6, 3)

arch/arm64/include/asm/sysreg.h

143

#define SYS_DC_IGDVAC sys_insn(1, 0, 7, 6, 5)

arch/arm64/include/asm/sysreg.h

145

#define SYS_DC_CVAC sys_insn(1, 3, 7, 10, 1)

arch/arm64/include/asm/sysreg.h

146

#define SYS_DC_CGVAC sys_insn(1, 3, 7, 10, 3)

arch/arm64/include/asm/sysreg.h

147

#define SYS_DC_CGDVAC sys_insn(1, 3, 7, 10, 5)

arch/arm64/include/asm/sysreg.h

149

#define SYS_DC_CVAU sys_insn(1, 3, 7, 11, 1)

arch/arm64/include/asm/sysreg.h

151

#define SYS_DC_CVAP sys_insn(1, 3, 7, 12, 1)

arch/arm64/include/asm/sysreg.h

152

#define SYS_DC_CGVAP sys_insn(1, 3, 7, 12, 3)

arch/arm64/include/asm/sysreg.h

153

#define SYS_DC_CGDVAP sys_insn(1, 3, 7, 12, 5)

arch/arm64/include/asm/sysreg.h

155

#define SYS_DC_CVADP sys_insn(1, 3, 7, 13, 1)

arch/arm64/include/asm/sysreg.h

156

#define SYS_DC_CGVADP sys_insn(1, 3, 7, 13, 3)

arch/arm64/include/asm/sysreg.h

157

#define SYS_DC_CGDVADP sys_insn(1, 3, 7, 13, 5)

arch/arm64/include/asm/sysreg.h

159

#define SYS_DC_CIVAC sys_insn(1, 3, 7, 14, 1)

arch/arm64/include/asm/sysreg.h

160

#define SYS_DC_CIGVAC sys_insn(1, 3, 7, 14, 3)

arch/arm64/include/asm/sysreg.h

161

#define SYS_DC_CIGDVAC sys_insn(1, 3, 7, 14, 5)

arch/arm64/include/asm/sysreg.h

163

#define SYS_DC_ZVA sys_insn(1, 3, 7, 4, 1)

arch/arm64/include/asm/sysreg.h

164

#define SYS_DC_GVA sys_insn(1, 3, 7, 4, 3)

arch/arm64/include/asm/sysreg.h

165

#define SYS_DC_GZVA sys_insn(1, 3, 7, 4, 4)

arch/arm64/include/asm/sysreg.h

167

#define SYS_DC_CIVAPS sys_insn(1, 0, 7, 15, 1)

arch/arm64/include/asm/sysreg.h

168

#define SYS_DC_CIGDVAPS sys_insn(1, 0, 7, 15, 5)

arch/arm64/include/asm/sysreg.h

632

#define OP_AT_S1E1R sys_insn(AT_Op0, 0, AT_CRn, 8, 0)

arch/arm64/include/asm/sysreg.h

633

#define OP_AT_S1E1W sys_insn(AT_Op0, 0, AT_CRn, 8, 1)

arch/arm64/include/asm/sysreg.h

634

#define OP_AT_S1E0R sys_insn(AT_Op0, 0, AT_CRn, 8, 2)

arch/arm64/include/asm/sysreg.h

635

#define OP_AT_S1E0W sys_insn(AT_Op0, 0, AT_CRn, 8, 3)

arch/arm64/include/asm/sysreg.h

636

#define OP_AT_S1E1RP sys_insn(AT_Op0, 0, AT_CRn, 9, 0)

arch/arm64/include/asm/sysreg.h

637

#define OP_AT_S1E1WP sys_insn(AT_Op0, 0, AT_CRn, 9, 1)

arch/arm64/include/asm/sysreg.h

638

#define OP_AT_S1E1A sys_insn(AT_Op0, 0, AT_CRn, 9, 2)

arch/arm64/include/asm/sysreg.h

639

#define OP_AT_S1E2R sys_insn(AT_Op0, 4, AT_CRn, 8, 0)

arch/arm64/include/asm/sysreg.h

640

#define OP_AT_S1E2W sys_insn(AT_Op0, 4, AT_CRn, 8, 1)

arch/arm64/include/asm/sysreg.h

641

#define OP_AT_S12E1R sys_insn(AT_Op0, 4, AT_CRn, 8, 4)

arch/arm64/include/asm/sysreg.h

642

#define OP_AT_S12E1W sys_insn(AT_Op0, 4, AT_CRn, 8, 5)

arch/arm64/include/asm/sysreg.h

643

#define OP_AT_S12E0R sys_insn(AT_Op0, 4, AT_CRn, 8, 6)

arch/arm64/include/asm/sysreg.h

644

#define OP_AT_S12E0W sys_insn(AT_Op0, 4, AT_CRn, 8, 7)

arch/arm64/include/asm/sysreg.h

645

#define OP_AT_S1E2A sys_insn(AT_Op0, 4, AT_CRn, 9, 2)

arch/arm64/include/asm/sysreg.h

665

#define OP_TLBI_VMALLE1OS sys_insn(1, 0, 8, 1, 0)

arch/arm64/include/asm/sysreg.h

666

#define OP_TLBI_VAE1OS sys_insn(1, 0, 8, 1, 1)

arch/arm64/include/asm/sysreg.h

667

#define OP_TLBI_ASIDE1OS sys_insn(1, 0, 8, 1, 2)

arch/arm64/include/asm/sysreg.h

668

#define OP_TLBI_VAAE1OS sys_insn(1, 0, 8, 1, 3)

arch/arm64/include/asm/sysreg.h

669

#define OP_TLBI_VALE1OS sys_insn(1, 0, 8, 1, 5)

arch/arm64/include/asm/sysreg.h

670

#define OP_TLBI_VAALE1OS sys_insn(1, 0, 8, 1, 7)

arch/arm64/include/asm/sysreg.h

671

#define OP_TLBI_RVAE1IS sys_insn(1, 0, 8, 2, 1)

arch/arm64/include/asm/sysreg.h

672

#define OP_TLBI_RVAAE1IS sys_insn(1, 0, 8, 2, 3)

arch/arm64/include/asm/sysreg.h

673

#define OP_TLBI_RVALE1IS sys_insn(1, 0, 8, 2, 5)

arch/arm64/include/asm/sysreg.h

674

#define OP_TLBI_RVAALE1IS sys_insn(1, 0, 8, 2, 7)

arch/arm64/include/asm/sysreg.h

675

#define OP_TLBI_VMALLE1IS sys_insn(1, 0, 8, 3, 0)

arch/arm64/include/asm/sysreg.h

676

#define OP_TLBI_VAE1IS sys_insn(1, 0, 8, 3, 1)

arch/arm64/include/asm/sysreg.h

677

#define OP_TLBI_ASIDE1IS sys_insn(1, 0, 8, 3, 2)

arch/arm64/include/asm/sysreg.h

678

#define OP_TLBI_VAAE1IS sys_insn(1, 0, 8, 3, 3)

arch/arm64/include/asm/sysreg.h

679

#define OP_TLBI_VALE1IS sys_insn(1, 0, 8, 3, 5)

arch/arm64/include/asm/sysreg.h

680

#define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7)

arch/arm64/include/asm/sysreg.h

681

#define OP_TLBI_RVAE1OS sys_insn(1, 0, 8, 5, 1)

arch/arm64/include/asm/sysreg.h

682

#define OP_TLBI_RVAAE1OS sys_insn(1, 0, 8, 5, 3)

arch/arm64/include/asm/sysreg.h

683

#define OP_TLBI_RVALE1OS sys_insn(1, 0, 8, 5, 5)

arch/arm64/include/asm/sysreg.h

684

#define OP_TLBI_RVAALE1OS sys_insn(1, 0, 8, 5, 7)

arch/arm64/include/asm/sysreg.h

685

#define OP_TLBI_RVAE1 sys_insn(1, 0, 8, 6, 1)

arch/arm64/include/asm/sysreg.h

686

#define OP_TLBI_RVAAE1 sys_insn(1, 0, 8, 6, 3)

arch/arm64/include/asm/sysreg.h

687

#define OP_TLBI_RVALE1 sys_insn(1, 0, 8, 6, 5)

arch/arm64/include/asm/sysreg.h

688

#define OP_TLBI_RVAALE1 sys_insn(1, 0, 8, 6, 7)

arch/arm64/include/asm/sysreg.h

689

#define OP_TLBI_VMALLE1 sys_insn(1, 0, 8, 7, 0)

arch/arm64/include/asm/sysreg.h

690

#define OP_TLBI_VAE1 sys_insn(1, 0, 8, 7, 1)

arch/arm64/include/asm/sysreg.h

691

#define OP_TLBI_ASIDE1 sys_insn(1, 0, 8, 7, 2)

arch/arm64/include/asm/sysreg.h

692

#define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3)

arch/arm64/include/asm/sysreg.h

693

#define OP_TLBI_VALE1 sys_insn(1, 0, 8, 7, 5)

arch/arm64/include/asm/sysreg.h

694

#define OP_TLBI_VAALE1 sys_insn(1, 0, 8, 7, 7)

arch/arm64/include/asm/sysreg.h

695

#define OP_TLBI_VMALLE1OSNXS sys_insn(1, 0, 9, 1, 0)

arch/arm64/include/asm/sysreg.h

696

#define OP_TLBI_VAE1OSNXS sys_insn(1, 0, 9, 1, 1)

arch/arm64/include/asm/sysreg.h

697

#define OP_TLBI_ASIDE1OSNXS sys_insn(1, 0, 9, 1, 2)

arch/arm64/include/asm/sysreg.h

698

#define OP_TLBI_VAAE1OSNXS sys_insn(1, 0, 9, 1, 3)

arch/arm64/include/asm/sysreg.h

699

#define OP_TLBI_VALE1OSNXS sys_insn(1, 0, 9, 1, 5)

arch/arm64/include/asm/sysreg.h

700

#define OP_TLBI_VAALE1OSNXS sys_insn(1, 0, 9, 1, 7)

arch/arm64/include/asm/sysreg.h

701

#define OP_TLBI_RVAE1ISNXS sys_insn(1, 0, 9, 2, 1)

arch/arm64/include/asm/sysreg.h

702

#define OP_TLBI_RVAAE1ISNXS sys_insn(1, 0, 9, 2, 3)

arch/arm64/include/asm/sysreg.h

703

#define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5)

arch/arm64/include/asm/sysreg.h

704

#define OP_TLBI_RVAALE1ISNXS sys_insn(1, 0, 9, 2, 7)

arch/arm64/include/asm/sysreg.h

705

#define OP_TLBI_VMALLE1ISNXS sys_insn(1, 0, 9, 3, 0)

arch/arm64/include/asm/sysreg.h

706

#define OP_TLBI_VAE1ISNXS sys_insn(1, 0, 9, 3, 1)

arch/arm64/include/asm/sysreg.h

707

#define OP_TLBI_ASIDE1ISNXS sys_insn(1, 0, 9, 3, 2)

arch/arm64/include/asm/sysreg.h

708

#define OP_TLBI_VAAE1ISNXS sys_insn(1, 0, 9, 3, 3)

arch/arm64/include/asm/sysreg.h

709

#define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5)

arch/arm64/include/asm/sysreg.h

710

#define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7)

arch/arm64/include/asm/sysreg.h

711

#define OP_TLBI_RVAE1OSNXS sys_insn(1, 0, 9, 5, 1)

arch/arm64/include/asm/sysreg.h

712

#define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3)

arch/arm64/include/asm/sysreg.h

713

#define OP_TLBI_RVALE1OSNXS sys_insn(1, 0, 9, 5, 5)

arch/arm64/include/asm/sysreg.h

714

#define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7)

arch/arm64/include/asm/sysreg.h

715

#define OP_TLBI_RVAE1NXS sys_insn(1, 0, 9, 6, 1)

arch/arm64/include/asm/sysreg.h

716

#define OP_TLBI_RVAAE1NXS sys_insn(1, 0, 9, 6, 3)

arch/arm64/include/asm/sysreg.h

717

#define OP_TLBI_RVALE1NXS sys_insn(1, 0, 9, 6, 5)

arch/arm64/include/asm/sysreg.h

718

#define OP_TLBI_RVAALE1NXS sys_insn(1, 0, 9, 6, 7)

arch/arm64/include/asm/sysreg.h

719

#define OP_TLBI_VMALLE1NXS sys_insn(1, 0, 9, 7, 0)

arch/arm64/include/asm/sysreg.h

720

#define OP_TLBI_VAE1NXS sys_insn(1, 0, 9, 7, 1)

arch/arm64/include/asm/sysreg.h

721

#define OP_TLBI_ASIDE1NXS sys_insn(1, 0, 9, 7, 2)

arch/arm64/include/asm/sysreg.h

722

#define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3)

arch/arm64/include/asm/sysreg.h

723

#define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5)

arch/arm64/include/asm/sysreg.h

724

#define OP_TLBI_VAALE1NXS sys_insn(1, 0, 9, 7, 7)

arch/arm64/include/asm/sysreg.h

725

#define OP_TLBI_IPAS2E1IS sys_insn(1, 4, 8, 0, 1)

arch/arm64/include/asm/sysreg.h

726

#define OP_TLBI_RIPAS2E1IS sys_insn(1, 4, 8, 0, 2)

arch/arm64/include/asm/sysreg.h

727

#define OP_TLBI_IPAS2LE1IS sys_insn(1, 4, 8, 0, 5)

arch/arm64/include/asm/sysreg.h

728

#define OP_TLBI_RIPAS2LE1IS sys_insn(1, 4, 8, 0, 6)

arch/arm64/include/asm/sysreg.h

729

#define OP_TLBI_ALLE2OS sys_insn(1, 4, 8, 1, 0)

arch/arm64/include/asm/sysreg.h

730

#define OP_TLBI_VAE2OS sys_insn(1, 4, 8, 1, 1)

arch/arm64/include/asm/sysreg.h

731

#define OP_TLBI_ALLE1OS sys_insn(1, 4, 8, 1, 4)

arch/arm64/include/asm/sysreg.h

732

#define OP_TLBI_VALE2OS sys_insn(1, 4, 8, 1, 5)

arch/arm64/include/asm/sysreg.h

733

#define OP_TLBI_VMALLS12E1OS sys_insn(1, 4, 8, 1, 6)

arch/arm64/include/asm/sysreg.h

734

#define OP_TLBI_RVAE2IS sys_insn(1, 4, 8, 2, 1)

arch/arm64/include/asm/sysreg.h

735

#define OP_TLBI_RVALE2IS sys_insn(1, 4, 8, 2, 5)

arch/arm64/include/asm/sysreg.h

736

#define OP_TLBI_ALLE2IS sys_insn(1, 4, 8, 3, 0)

arch/arm64/include/asm/sysreg.h

737

#define OP_TLBI_VAE2IS sys_insn(1, 4, 8, 3, 1)

arch/arm64/include/asm/sysreg.h

738

#define OP_TLBI_ALLE1IS sys_insn(1, 4, 8, 3, 4)

arch/arm64/include/asm/sysreg.h

739

#define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5)

arch/arm64/include/asm/sysreg.h

740

#define OP_TLBI_VMALLS12E1IS sys_insn(1, 4, 8, 3, 6)

arch/arm64/include/asm/sysreg.h

741

#define OP_TLBI_IPAS2E1OS sys_insn(1, 4, 8, 4, 0)

arch/arm64/include/asm/sysreg.h

742

#define OP_TLBI_IPAS2E1 sys_insn(1, 4, 8, 4, 1)

arch/arm64/include/asm/sysreg.h

743

#define OP_TLBI_RIPAS2E1 sys_insn(1, 4, 8, 4, 2)

arch/arm64/include/asm/sysreg.h

744

#define OP_TLBI_RIPAS2E1OS sys_insn(1, 4, 8, 4, 3)

arch/arm64/include/asm/sysreg.h

745

#define OP_TLBI_IPAS2LE1OS sys_insn(1, 4, 8, 4, 4)

arch/arm64/include/asm/sysreg.h

746

#define OP_TLBI_IPAS2LE1 sys_insn(1, 4, 8, 4, 5)

arch/arm64/include/asm/sysreg.h

747

#define OP_TLBI_RIPAS2LE1 sys_insn(1, 4, 8, 4, 6)

arch/arm64/include/asm/sysreg.h

748

#define OP_TLBI_RIPAS2LE1OS sys_insn(1, 4, 8, 4, 7)

arch/arm64/include/asm/sysreg.h

749

#define OP_TLBI_RVAE2OS sys_insn(1, 4, 8, 5, 1)

arch/arm64/include/asm/sysreg.h

750

#define OP_TLBI_RVALE2OS sys_insn(1, 4, 8, 5, 5)

arch/arm64/include/asm/sysreg.h

751

#define OP_TLBI_RVAE2 sys_insn(1, 4, 8, 6, 1)

arch/arm64/include/asm/sysreg.h

752

#define OP_TLBI_RVALE2 sys_insn(1, 4, 8, 6, 5)

arch/arm64/include/asm/sysreg.h

753

#define OP_TLBI_ALLE2 sys_insn(1, 4, 8, 7, 0)

arch/arm64/include/asm/sysreg.h

754

#define OP_TLBI_VAE2 sys_insn(1, 4, 8, 7, 1)

arch/arm64/include/asm/sysreg.h

755

#define OP_TLBI_ALLE1 sys_insn(1, 4, 8, 7, 4)

arch/arm64/include/asm/sysreg.h

756

#define OP_TLBI_VALE2 sys_insn(1, 4, 8, 7, 5)

arch/arm64/include/asm/sysreg.h

757

#define OP_TLBI_VMALLS12E1 sys_insn(1, 4, 8, 7, 6)

arch/arm64/include/asm/sysreg.h

758

#define OP_TLBI_IPAS2E1ISNXS sys_insn(1, 4, 9, 0, 1)

arch/arm64/include/asm/sysreg.h

759

#define OP_TLBI_RIPAS2E1ISNXS sys_insn(1, 4, 9, 0, 2)

arch/arm64/include/asm/sysreg.h

760

#define OP_TLBI_IPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 5)

arch/arm64/include/asm/sysreg.h

761

#define OP_TLBI_RIPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 6)

arch/arm64/include/asm/sysreg.h

762

#define OP_TLBI_ALLE2OSNXS sys_insn(1, 4, 9, 1, 0)

arch/arm64/include/asm/sysreg.h

763

#define OP_TLBI_VAE2OSNXS sys_insn(1, 4, 9, 1, 1)

arch/arm64/include/asm/sysreg.h

764

#define OP_TLBI_ALLE1OSNXS sys_insn(1, 4, 9, 1, 4)

arch/arm64/include/asm/sysreg.h

765

#define OP_TLBI_VALE2OSNXS sys_insn(1, 4, 9, 1, 5)

arch/arm64/include/asm/sysreg.h

766

#define OP_TLBI_VMALLS12E1OSNXS sys_insn(1, 4, 9, 1, 6)

arch/arm64/include/asm/sysreg.h

767

#define OP_TLBI_RVAE2ISNXS sys_insn(1, 4, 9, 2, 1)

arch/arm64/include/asm/sysreg.h

768

#define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5)

arch/arm64/include/asm/sysreg.h

769

#define OP_TLBI_ALLE2ISNXS sys_insn(1, 4, 9, 3, 0)

arch/arm64/include/asm/sysreg.h

770

#define OP_TLBI_VAE2ISNXS sys_insn(1, 4, 9, 3, 1)

arch/arm64/include/asm/sysreg.h

771

#define OP_TLBI_ALLE1ISNXS sys_insn(1, 4, 9, 3, 4)

arch/arm64/include/asm/sysreg.h

772

#define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5)

arch/arm64/include/asm/sysreg.h

773

#define OP_TLBI_VMALLS12E1ISNXS sys_insn(1, 4, 9, 3, 6)

arch/arm64/include/asm/sysreg.h

774

#define OP_TLBI_IPAS2E1OSNXS sys_insn(1, 4, 9, 4, 0)

arch/arm64/include/asm/sysreg.h

775

#define OP_TLBI_IPAS2E1NXS sys_insn(1, 4, 9, 4, 1)

arch/arm64/include/asm/sysreg.h

776

#define OP_TLBI_RIPAS2E1NXS sys_insn(1, 4, 9, 4, 2)

arch/arm64/include/asm/sysreg.h

777

#define OP_TLBI_RIPAS2E1OSNXS sys_insn(1, 4, 9, 4, 3)

arch/arm64/include/asm/sysreg.h

778

#define OP_TLBI_IPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 4)

arch/arm64/include/asm/sysreg.h

779

#define OP_TLBI_IPAS2LE1NXS sys_insn(1, 4, 9, 4, 5)

arch/arm64/include/asm/sysreg.h

780

#define OP_TLBI_RIPAS2LE1NXS sys_insn(1, 4, 9, 4, 6)

arch/arm64/include/asm/sysreg.h

781

#define OP_TLBI_RIPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 7)

arch/arm64/include/asm/sysreg.h

782

#define OP_TLBI_RVAE2OSNXS sys_insn(1, 4, 9, 5, 1)

arch/arm64/include/asm/sysreg.h

783

#define OP_TLBI_RVALE2OSNXS sys_insn(1, 4, 9, 5, 5)

arch/arm64/include/asm/sysreg.h

784

#define OP_TLBI_RVAE2NXS sys_insn(1, 4, 9, 6, 1)

arch/arm64/include/asm/sysreg.h

785

#define OP_TLBI_RVALE2NXS sys_insn(1, 4, 9, 6, 5)

arch/arm64/include/asm/sysreg.h

786

#define OP_TLBI_ALLE2NXS sys_insn(1, 4, 9, 7, 0)

arch/arm64/include/asm/sysreg.h

787

#define OP_TLBI_VAE2NXS sys_insn(1, 4, 9, 7, 1)

arch/arm64/include/asm/sysreg.h

788

#define OP_TLBI_ALLE1NXS sys_insn(1, 4, 9, 7, 4)

arch/arm64/include/asm/sysreg.h

789

#define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)

arch/arm64/include/asm/sysreg.h

790

#define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6)

arch/arm64/include/asm/sysreg.h

793

#define OP_GCSPUSHX sys_insn(1, 0, 7, 7, 4)

arch/arm64/include/asm/sysreg.h

794

#define OP_GCSPOPCX sys_insn(1, 0, 7, 7, 5)

arch/arm64/include/asm/sysreg.h

795

#define OP_GCSPOPX sys_insn(1, 0, 7, 7, 6)

arch/arm64/include/asm/sysreg.h

796

#define OP_GCSPUSHM sys_insn(1, 3, 7, 7, 0)

arch/arm64/include/asm/sysreg.h

798

#define OP_BRB_IALL sys_insn(1, 1, 7, 2, 4)

arch/arm64/include/asm/sysreg.h

799

#define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5)

arch/arm64/include/asm/sysreg.h

800

#define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4)

arch/arm64/include/asm/sysreg.h

801

#define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5)

arch/arm64/include/asm/sysreg.h

802

#define OP_COSP_RCTX sys_insn(1, 3, 7, 3, 6)

arch/arm64/include/asm/sysreg.h

803

#define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7)

arch/arm64/kvm/sys_regs.c

3790

u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);

arch/arm64/kvm/sys_regs.c

3801

u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);

arch/arm64/kvm/sys_regs.c

3819

u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);