ssd2825_write_reg
ret = ssd2825_write_reg(priv, SSD2825_PACKET_SIZE_CTRL_REG_1, len);
ret = ssd2825_write_reg(priv, SSD2825_SPI_READ_REG, SSD2825_SPI_READ_REG_RESET);
ret = ssd2825_write_reg(priv, SSD2825_CONFIGURATION_REG, config);
ret = ssd2825_write_reg(priv, SSD2825_VC_CTRL_REG, 0x0000);
ssd2825_write_reg(priv, SSD2825_PLL_CTRL_REG, 0x0000);
ssd2825_write_reg(priv, SSD2825_LINE_CTRL_REG, 0x0001);
ssd2825_write_reg(priv, SSD2825_DELAY_ADJ_REG_1, (hzd << 8) | hpd);
ssd2825_write_reg(priv, SSD2825_PLL_CONFIGURATION_REG, pll_config);
ssd2825_write_reg(priv, SSD2825_CLOCK_CTRL_REG,
ssd2825_write_reg(priv, SSD2825_PLL_CTRL_REG, 0x0001);
ssd2825_write_reg(priv, SSD2825_VC_CTRL_REG, 0);
ssd2825_write_reg(priv, SSD2825_OPERATION_CTRL_REG, 0x0100);
ssd2825_write_reg(priv, SSD2825_RGB_INTERFACE_CTRL_REG_1,
ssd2825_write_reg(priv, SSD2825_RGB_INTERFACE_CTRL_REG_2,
ssd2825_write_reg(priv, SSD2825_RGB_INTERFACE_CTRL_REG_3,
ssd2825_write_reg(priv, SSD2825_RGB_INTERFACE_CTRL_REG_4, mode->hdisplay);
ssd2825_write_reg(priv, SSD2825_RGB_INTERFACE_CTRL_REG_5, mode->vdisplay);
ssd2825_write_reg(priv, SSD2825_RGB_INTERFACE_CTRL_REG_6, flags | pixel_format);
ssd2825_write_reg(priv, SSD2825_LANE_CONFIGURATION_REG, dsi_dev->lanes - 1);
ssd2825_write_reg(priv, SSD2825_TEST_REG, 0x0004);
ssd2825_write_reg(priv, SSD2825_CONFIGURATION_REG, config);
ssd2825_write_reg(priv, SSD2825_VC_CTRL_REG, 0);
ssd2825_write_reg(priv, SSD2825_CONFIGURATION_REG, config);
ssd2825_write_reg(priv, SSD2825_PLL_CTRL_REG, 0x0001);
ssd2825_write_reg(priv, SSD2825_VC_CTRL_REG, 0x0000);
ssd2825_write_reg(priv, SSD2825_CONFIGURATION_REG,
ssd2825_write_reg(priv, SSD2825_VC_CTRL_REG, 0);