ssb_read32
return ssb_read32(bp->sdev, reg);
return ssb_read32(dev->sdev, offset);
ssb_read32(dev->dev->sdev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64))
tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
(ssb_read32(gpiodev, B43_GPIO_CONTROL)
tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */
tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */
tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
return ssb_read32(dev->dev, offset);
(ssb_read32(gpiodev, B43legacy_GPIO_CONTROL)
value32 = ssb_read32(dev->dev, SSB_TMSLOW);
tmslow = ssb_read32(sdev, SSB_TMSLOW);
tmslow = ssb_read32(sdev, SSB_TMSLOW);
tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
return ssb_read32(extif->dev, offset);
base = ssb_admatch_base(ssb_read32(sdev, SSB_ADMATCH1));
tmslow = ssb_read32(sdev, SSB_TMSLOW);
tmshigh = ssb_read32(sdev, SSB_TMSHIGH);
return ssb_read32(dev->dev, offset);
u32 val = ssb_read32(extif->dev, SSB_EXTIF_GPIO_IN);
u32 mask = ssb_read32(extif->dev, SSB_EXTIF_GPIO_INTMASK);
u32 pol = ssb_read32(extif->dev, SSB_EXTIF_GPIO_INTPOL);
ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);
if ((1 << irqflag) & ssb_read32(mdev, SSB_INTVEC))
ssb_read32(dev, SSB_IPSFLAG) |
ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) | ssb_read32(mdev, SSB_INTVEC)));
u32 ipsflag = ssb_read32(mdev, SSB_IPSFLAG);
if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
return ssb_read32(mcore->dev, offset);
u32 tpsflag = ssb_read32(dev, SSB_TPSFLAG);
return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
return ssb_read32(pc->dev, offset);
tmp = ssb_read32(pdev, SSB_IMCFGLO);
intvec = ssb_read32(pdev, SSB_INTVEC);
tmp = ssb_read32(dev, SSB_TPSFLAG);
val = ssb_read32(dev, SSB_TMSLOW);
ssb_read32(dev, SSB_TMSLOW);
if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
val = ssb_read32(dev, SSB_IMSTATE);
val = ssb_read32(dev, reg);
if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
val = ssb_read32(dev, SSB_IMSTATE);
if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
val = ssb_read32(dev, SSB_IMSTATE);
ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
tmp = ssb_read32(dev, SSB_ADMATCH0);
ssb_write32(dev, 0x89c, ssb_read32(dev, 0x89c) | 0x1);
ssb_write32(dev, 0x400, ssb_read32(dev, 0x400) & ~8);
ssb_read32(dev, 0x400);
ssb_write32(dev, 0x304, ssb_read32(dev, 0x304) & ~0x100);
ssb_read32(dev, 0x304);
#define chipco_read32(cc, offset) ssb_read32((cc)->dev, offset)