ssb_chipco_pll_write
ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL0, pllctl);
ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL1, pllctl);
ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL2, pllctl);
ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, pllctl);
ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, pllctl);
ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, pllctl);
ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, pllctl);
ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100070);
ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x1014140a);
ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888854);
ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05201828);
ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05001828);
ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11500008);
ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0C000C06);
ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x0F600a08);
ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000);
ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x2001E920);
ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888815);
ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100008);
ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0c000c06);
ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x03000a08);
ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000);
ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x200005c0);
ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888855);