src_writel
src_writel(dev, MUnit.ODR_C,
src_writel(dev, MUnit.IDR, 1 << 23);
src_writel(dev, MUnit.ODR_C, 0xffffffff);
src_writel(dev,
src_writel(dev,
src_writel(dev, MUnit.IDR, val);
src_writel(dev, MUnit.IOAR, val);
src_writel(dev,
src_writel(dev, MUnit.IDR, val);
src_writel(dev, MUnit.IDR, val);
src_writel(dev, MUnit.IDR, val);
src_writel(dev, MUnit.IDR, val);
src_writel(dev, MUnit.IOAR, val);
src_writel(dev, MUnit.OIMR,
src_writel(dev, MUnit.OIMR, dev->OIMR = 0xffffffff);
src_writel(dev,
src_writel(dev, MUnit.OIMR, dev->OIMR = 0xffffffff);
src_writel(dev, MUnit.IDR, INBOUNDDOORBELL_0 << SRC_IDR_SHIFT);
src_writel(dev,
src_writel(dev,
src_writel(dev, MUnit.ODR_C,
src_writel(dev, MUnit.ODR_C,
src_writel(dev, MUnit.ODR_C,
src_writel(dev, MUnit.ODR_C,
src_writel(dev, MUnit.ODR_C,
src_writel(dev, MUnit.ODR_C,
src_writel(dev, MUnit.IQN_H,
src_writel(dev, MUnit.IQN_L, address & 0xffffffff);
src_writel(dev, MUnit.IQ_H,
src_writel(dev, MUnit.IQ_L, address & 0xffffffff);
src_writel(dev, MUnit.ODR_C, bellbits);
src_writel(dev, MUnit.ODR_C, bellbits);
src_writel(dev, MUnit.OMR, omr_value & AAC_INT_MODE_MSIX);
src_writel(dev, MUnit.IDR, IOP_SRC_RESET_MASK);
src_writel(dev, MUnit.ODR_C, bellbits);
src_writel(dev, MUnit.ODR_C, 0xffffffff);