arch/powerpc/platforms/cell/spu_base.c

296

spu_int_stat_clear(spu, 0, stat);

arch/powerpc/platforms/cell/spu_base.c

318

spu_int_stat_clear(spu, 1, stat);

arch/powerpc/platforms/cell/spu_base.c

357

spu_int_stat_clear(spu, 2, stat);

arch/powerpc/platforms/cell/spufs/hw_ops.c

64

spu_int_stat_clear(spu, 2, CLASS2_MAILBOX_INTR);

arch/powerpc/platforms/cell/spufs/hw_ops.c

72

spu_int_stat_clear(spu, 2,

arch/powerpc/platforms/cell/spufs/switch.c

1410

spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);

arch/powerpc/platforms/cell/spufs/switch.c

1411

spu_int_stat_clear(spu, 1, CLASS1_INTR_MASK);

arch/powerpc/platforms/cell/spufs/switch.c

1412

spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);

arch/powerpc/platforms/cell/spufs/switch.c

1682

spu_int_stat_clear(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);

arch/powerpc/platforms/cell/spufs/switch.c

755

spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);

arch/powerpc/platforms/cell/spufs/switch.c

756

spu_int_stat_clear(spu, 1, CLASS1_INTR_MASK);

arch/powerpc/platforms/cell/spufs/switch.c

757

spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);

arch/powerpc/platforms/cell/spufs/switch.c

914

spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);

arch/powerpc/platforms/cell/spufs/switch.c

915

spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);

arch/powerpc/platforms/cell/spufs/switch.c

933

spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);

arch/powerpc/platforms/cell/spufs/switch.c

934

spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);