arch/x86/kvm/svm/avic.c

155

svm_set_intercept_for_msr(&svm->vcpu, x2avic_passthrough_msrs[i],

arch/x86/kvm/svm/sev.c

4562

svm_set_intercept_for_msr(vcpu, MSR_TSC_AUX, MSR_TYPE_RW,

arch/x86/kvm/svm/sev.c

4566

svm_set_intercept_for_msr(vcpu, MSR_AMD64_GUEST_TSC_FREQ, MSR_TYPE_R,

arch/x86/kvm/svm/sev.c

4581

svm_set_intercept_for_msr(vcpu, MSR_IA32_XSS, MSR_TYPE_RW,

arch/x86/kvm/svm/svm.c

718

svm_set_intercept_for_msr(vcpu, MSR_IA32_LASTBRANCHFROMIP, MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

719

svm_set_intercept_for_msr(vcpu, MSR_IA32_LASTBRANCHTOIP, MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

720

svm_set_intercept_for_msr(vcpu, MSR_IA32_LASTINTFROMIP, MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

721

svm_set_intercept_for_msr(vcpu, MSR_IA32_LASTINTTOIP, MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

724

svm_set_intercept_for_msr(vcpu, MSR_IA32_DEBUGCTLMSR, MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

745

svm_set_intercept_for_msr(vcpu, MSR_K7_PERFCTR0 + i,

arch/x86/kvm/svm/svm.c

750

svm_set_intercept_for_msr(vcpu, MSR_F15H_PERF_CTR + 2 * i,

arch/x86/kvm/svm/svm.c

758

svm_set_intercept_for_msr(vcpu, MSR_AMD64_PERF_CNTR_GLOBAL_CTL,

arch/x86/kvm/svm/svm.c

760

svm_set_intercept_for_msr(vcpu, MSR_AMD64_PERF_CNTR_GLOBAL_STATUS,

arch/x86/kvm/svm/svm.c

762

svm_set_intercept_for_msr(vcpu, MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR,

arch/x86/kvm/svm/svm.c

764

svm_set_intercept_for_msr(vcpu, MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET,

arch/x86/kvm/svm/svm.c

788

svm_set_intercept_for_msr(vcpu, MSR_IA32_PRED_CMD, MSR_TYPE_W,

arch/x86/kvm/svm/svm.c

792

svm_set_intercept_for_msr(vcpu, MSR_IA32_FLUSH_CMD, MSR_TYPE_W,

arch/x86/kvm/svm/svm.c

802

svm_set_intercept_for_msr(vcpu, MSR_IA32_SPEC_CTRL, MSR_TYPE_RW,

arch/x86/kvm/svm/svm.c

805

svm_set_intercept_for_msr(vcpu, MSR_IA32_SPEC_CTRL, MSR_TYPE_RW,

arch/x86/kvm/svm/svm.c

812

svm_set_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW,

arch/x86/kvm/svm/svm.c

814

svm_set_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW,

arch/x86/kvm/svm/svm.c

825

svm_set_intercept_for_msr(vcpu, MSR_IA32_U_CET, MSR_TYPE_RW, !shstk_enabled);

arch/x86/kvm/svm/svm.c

826

svm_set_intercept_for_msr(vcpu, MSR_IA32_S_CET, MSR_TYPE_RW, !shstk_enabled);

arch/x86/kvm/svm/svm.c

827

svm_set_intercept_for_msr(vcpu, MSR_IA32_PL0_SSP, MSR_TYPE_RW, !shstk_enabled);

arch/x86/kvm/svm/svm.c

828

svm_set_intercept_for_msr(vcpu, MSR_IA32_PL1_SSP, MSR_TYPE_RW, !shstk_enabled);

arch/x86/kvm/svm/svm.c

829

svm_set_intercept_for_msr(vcpu, MSR_IA32_PL2_SSP, MSR_TYPE_RW, !shstk_enabled);

arch/x86/kvm/svm/svm.c

830

svm_set_intercept_for_msr(vcpu, MSR_IA32_PL3_SSP, MSR_TYPE_RW, !shstk_enabled);

arch/x86/kvm/svm/svm.h

735

void svm_set_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type, bool set);

arch/x86/kvm/svm/svm.h

740

svm_set_intercept_for_msr(vcpu, msr, type, false);

arch/x86/kvm/svm/svm.h

746

svm_set_intercept_for_msr(vcpu, msr, type, true);