spi_engine
struct spi_engine *spi_engine = priv->spi_engine;
spi_engine->base + SPI_ENGINE_REG_CMD_FIFO);
spi_engine->base + SPI_ENGINE_REG_CMD_FIFO);
spi_engine->base + SPI_ENGINE_REG_CMD_FIFO);
spi_engine->base + SPI_ENGINE_REG_CMD_FIFO);
spi_engine->base + SPI_ENGINE_REG_CMD_FIFO);
spi_engine->base + SPI_ENGINE_REG_CMD_FIFO);
ret = readl_relaxed_poll_timeout(spi_engine->base + SPI_ENGINE_REG_SYNC_ID,
reg = readl_relaxed(spi_engine->base +
writel_relaxed(reg, spi_engine->base +
struct spi_engine *spi_engine = priv->spi_engine;
reg = readl_relaxed(spi_engine->base +
writel_relaxed(reg, spi_engine->base +
spi_engine->base + SPI_ENGINE_REG_CMD_FIFO);
spi_engine->base + SPI_ENGINE_REG_CMD_FIFO);
struct spi_engine *spi_engine = p;
writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
writel_relaxed(0x01, spi_engine->base + SPI_ENGINE_REG_RESET);
struct spi_engine *spi_engine;
host = devm_spi_alloc_host(&pdev->dev, sizeof(*spi_engine));
spi_engine = spi_controller_get_devdata(host);
spin_lock_init(&spi_engine->lock);
init_completion(&spi_engine->msg_complete);
spi_engine->offload =
if (IS_ERR(spi_engine->offload))
return PTR_ERR(spi_engine->offload);
priv = spi_engine->offload->priv;
priv->spi_engine = spi_engine;
spi_engine->offload->ops = &spi_engine_offload_ops;
spi_engine->offload_caps = SPI_OFFLOAD_CAP_TRIGGER;
spi_engine->offload_caps |= SPI_OFFLOAD_CAP_RX_STREAM_DMA;
spi_engine->offload->xfer_flags |= SPI_OFFLOAD_XFER_RX_STREAM;
spi_engine->offload_caps |= SPI_OFFLOAD_CAP_TX_STREAM_DMA;
spi_engine->offload->xfer_flags |= SPI_OFFLOAD_XFER_TX_STREAM;
spi_engine->offload_caps |= SPI_OFFLOAD_CAP_TX_STATIC_DATA;
spi_engine->clk = devm_clk_get_enabled(&pdev->dev, "s_axi_aclk");
if (IS_ERR(spi_engine->clk))
return PTR_ERR(spi_engine->clk);
spi_engine->ref_clk = devm_clk_get_enabled(&pdev->dev, "spi_clk");
if (IS_ERR(spi_engine->ref_clk))
return PTR_ERR(spi_engine->ref_clk);
spi_engine->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(spi_engine->base))
return PTR_ERR(spi_engine->base);
version = readl(spi_engine->base + ADI_AXI_REG_VERSION);
data_width_reg_val = readl(spi_engine->base + SPI_ENGINE_REG_DATA_WIDTH);
unsigned int sizes = readl(spi_engine->base +
spi_engine->offload_ctrl_mem_size = 1 <<
spi_engine->offload_sdo_mem_size = 1 <<
spi_engine->offload_ctrl_mem_size = SPI_ENGINE_OFFLOAD_CMD_FIFO_SIZE;
spi_engine->offload_sdo_mem_size = SPI_ENGINE_OFFLOAD_SDO_FIFO_SIZE;
spi_engine->offload_requires_sync = !adi_axi_pcore_ver_gteq(version, 1, 5);
writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_RESET);
writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
spi_engine);
host->max_speed_hz = clk_get_rate(spi_engine->ref_clk) / 2;
struct spi_engine *spi_engine;
static bool spi_engine_write_cmd_fifo(struct spi_engine *spi_engine,
void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_CMD_FIFO;
n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_CMD_FIFO_ROOM);
static bool spi_engine_write_tx_fifo(struct spi_engine *spi_engine,
void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_SDO_DATA_FIFO;
n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_SDO_FIFO_ROOM);
static bool spi_engine_read_rx_fifo(struct spi_engine *spi_engine,
void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_SDI_DATA_FIFO;
n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_SDI_FIFO_LEVEL);
struct spi_engine *spi_engine = spi_controller_get_devdata(host);
pending = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
spi_engine->base + SPI_ENGINE_REG_SYNC_ID);
spin_lock(&spi_engine->lock);
if (!spi_engine_write_cmd_fifo(spi_engine, msg))
if (!spi_engine_write_tx_fifo(spi_engine, msg))
if (!spi_engine_read_rx_fifo(spi_engine, msg))
complete(&spi_engine->msg_complete);
spi_engine->int_enable &= ~disable_int;
writel_relaxed(spi_engine->int_enable,
spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
spin_unlock(&spi_engine->lock);
struct spi_engine *spi_engine = spi_controller_get_devdata(host);
if (p->length > spi_engine->offload_ctrl_mem_size)
if (tx_word_count && !(spi_engine->offload_caps & SPI_OFFLOAD_CAP_TX_STATIC_DATA))
if (tx_word_count > spi_engine->offload_sdo_mem_size)
cmd_addr = spi_engine->base +
sdo_addr = spi_engine->base +
struct spi_engine *spi_engine = priv->spi_engine;
writel_relaxed(1, spi_engine->base +
writel_relaxed(0, spi_engine->base +
struct spi_engine *spi_engine = spi_controller_get_devdata(host);
if (!msg->offload || spi_engine->offload_requires_sync)
struct spi_engine *spi_engine = spi_controller_get_devdata(host);
if (!spi_engine->offload)
if (config->capability_flags & ~spi_engine->offload_caps)
priv = spi_engine->offload->priv;
return spi_engine->offload;
struct spi_engine *spi_engine = spi_controller_get_devdata(host);
spi_engine->cs_inv |= BIT(spi_get_chipselect(device, 0));
spi_engine->cs_inv &= ~BIT(spi_get_chipselect(device, 0));
spi_engine->base + SPI_ENGINE_REG_CMD_FIFO);
writel_relaxed(SPI_ENGINE_CMD_CS_INV(spi_engine->cs_inv),
spi_engine->base + SPI_ENGINE_REG_CMD_FIFO);
spi_engine->base + SPI_ENGINE_REG_CMD_FIFO);
spi_engine->base + SPI_ENGINE_REG_CMD_FIFO);
spi_engine->base + SPI_ENGINE_REG_CMD_FIFO);
spi_engine->base + SPI_ENGINE_REG_CMD_FIFO);
return readl_relaxed_poll_timeout(spi_engine->base + SPI_ENGINE_REG_SYNC_ID,
struct spi_engine *spi_engine = spi_controller_get_devdata(host);
struct spi_engine_message_state *st = &spi_engine->msg_state;
reinit_completion(&spi_engine->msg_complete);
spin_lock_irqsave(&spi_engine->lock, flags);
if (spi_engine_write_cmd_fifo(spi_engine, msg))
if (spi_engine_write_tx_fifo(spi_engine, msg))
spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
spi_engine->int_enable = int_enable;
spin_unlock_irqrestore(&spi_engine->lock, flags);
if (!wait_for_completion_timeout(&spi_engine->msg_complete,