drivers/clk/clk-axi-clkgen.c

508

unsigned int tech, family, speed_grade, reg_value;

drivers/clk/clk-axi-clkgen.c

513

speed_grade = ADI_AXI_INFO_FPGA_SPEED_GRADE(reg_value);

drivers/clk/clk-axi-clkgen.c

518

switch (speed_grade) {

drivers/clk/clk-axi-clkgen.c

541

speed_grade);

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

1186

ret = of_property_read_u32(np, "xlnx,speed-grade", &clk_wzrd->speed_grade);

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

1188

if (clk_wzrd->speed_grade < 1 || clk_wzrd->speed_grade > 3) {

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

1190

clk_wzrd->speed_grade);

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

1191

clk_wzrd->speed_grade = 0;

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

1212

if (clk_wzrd->speed_grade) {

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

142

unsigned int speed_grade;

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

940

max = clk_wzrd_max_freq[clk_wzrd->speed_grade - 1];

drivers/cpufreq/imx-cpufreq-dt.c

122

speed_grade = (cell_value & IMX8MN_OCOTP_CFG3_SPEED_GRADE_MASK)

drivers/cpufreq/imx-cpufreq-dt.c

125

speed_grade = (cell_value & OCOTP_CFG3_SPEED_GRADE_MASK)

drivers/cpufreq/imx-cpufreq-dt.c

142

if (mkt_segment == 0 && speed_grade == 0) {

drivers/cpufreq/imx-cpufreq-dt.c

145

speed_grade = 1;

drivers/cpufreq/imx-cpufreq-dt.c

148

speed_grade = 0xb;

drivers/cpufreq/imx-cpufreq-dt.c

151

supported_hw[0] = BIT(speed_grade);

drivers/cpufreq/imx-cpufreq-dt.c

154

speed_grade, mkt_segment, supported_hw[0], supported_hw[1]);

drivers/cpufreq/imx-cpufreq-dt.c

87

int speed_grade, mkt_segment;

drivers/misc/genwqe/card_utils.c

1017

static const int speed_grade[] = { 250, 200, 166, 175 };

drivers/misc/genwqe/card_utils.c

1020

if (speed >= ARRAY_SIZE(speed_grade))

drivers/misc/genwqe/card_utils.c

1023

return speed_grade[speed];