stv0900_read_reg
intp->chip_id = stv0900_read_reg(intp, R0900_MID);
selosci = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL);
tsbitrate0_val = stv0900_read_reg(intp, TSBITRATE0);
tsbitrate1_val = stv0900_read_reg(intp, TSBITRATE1);
reply->msg[i] = stv0900_read_reg(intp, DISRXDATA);
reg = stv0900_read_reg(intp, (label >> 16) & 0xffff);
val = stv0900_read_reg(intp, label >> 16);
intp->chip_id = stv0900_read_reg(intp, R0900_MID);
i = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL);
if (stv0900_read_reg(intp, R0900_MID) >= 0x20) {
err_val1 = stv0900_read_reg(intp, BBFCRCKO1);
err_val0 = stv0900_read_reg(intp, BBFCRCKO0);
err_val1 = stv0900_read_reg(intp, UPCRCKO1);
err_val0 = stv0900_read_reg(intp, UPCRCKO0);
mod_code = stv0900_read_reg(intp, PLHMODCOD);
extern u8 stv0900_read_reg(struct stv0900_internal *i_params,
timing = stv0900_read_reg(intp, TMGREG2);
timing = stv0900_read_reg(intp, TMGREG2);
freq1 = stv0900_read_reg(intp, CFR2);
freq0 = stv0900_read_reg(intp, CFR1);
agc2level += (stv0900_read_reg(intp, AGC2I1) << 8)
| stv0900_read_reg(intp, AGC2I0);
agc2_integr += (stv0900_read_reg(intp, AGC2I1) << 8) |
stv0900_read_reg(intp, AGC2I0);
coarse_freq = (stv0900_read_reg(intp, CFR2) << 8)
| stv0900_read_reg(intp, CFR1);
agc2_int = (stv0900_read_reg(intp, AGC2I1) << 8)
| stv0900_read_reg(intp, AGC2I0);
dstatus2 = stv0900_read_reg(intp, DSTATUS2);
carr_offset = (stv0900_read_reg(intp, CFR2) << 8)
| stv0900_read_reg(intp, CFR1);
agc2_integr = (stv0900_read_reg(intp, AGC2I1) << 8)
| stv0900_read_reg(intp, AGC2I0);
timingoffset = (stv0900_read_reg(intp, TMGREG2) << 16) +
(stv0900_read_reg(intp, TMGREG2 + 1) << 8) +
(stv0900_read_reg(intp, TMGREG2 + 2));
rolloff = stv0900_read_reg(intp, MATSTR1) & 0x03;
car_freq = stv0900_read_reg(intp, CARFREQ);
tmg_th_high = stv0900_read_reg(intp, TMGTHRISE);
tmg_th_low = stv0900_read_reg(intp, TMGTHFALL);
freq1 = stv0900_read_reg(intp, CFR2);
freq0 = stv0900_read_reg(intp, CFR1);