stv0367_writereg
stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x64);
stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x8a);
stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x6e);
stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xb7);
stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x9d);
stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x82);
stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa5);
stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x99);
stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x76);
stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xb1);
stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0x97);
stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x8e);
stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x94);
stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x85);
stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
stv0367_writereg(state, R367CAB_MIX_NCO_LL, sampled_if);
stv0367_writereg(state, R367CAB_MIX_NCO_HL, (sampled_if >> 8));
stv0367_writereg(state, R367CAB_EQU_CRL_TFR, (u8)u32_tmp);
stv0367_writereg(state, (label >> 16) & 0xffff, reg);
stv0367_writereg(state, R367CAB_SRC_NCO_LL, u32_tmp);
stv0367_writereg(state, R367CAB_SRC_NCO_LH, (u32_tmp >> 8));
stv0367_writereg(state, R367CAB_SRC_NCO_HL, (u32_tmp >> 16));
stv0367_writereg(state, R367CAB_SRC_NCO_HH, (u32_tmp >> 24));
stv0367_writereg(state, R367CAB_IQDEM_GAIN_SRC_L, u32_tmp1 & 0x00ff);
stv0367_writereg(state, R367CAB_ANACTRL, 0x00);/*PLL enabled and used */
stv0367_writereg(state, R367CAB_CTRL_1, 0x04);
stv0367_writereg(state, R367CAB_CTRL_1, 0x00);
stv0367_writereg(state, deftab[i].addr, deftab[i].value);
stv0367_writereg(state, R367TER_PLLMDIV, 0x1b);
stv0367_writereg(state, R367TER_PLLNDIV, 0xe8);
stv0367_writereg(state, R367TER_PLLMDIV, 0x2);
stv0367_writereg(state, R367TER_PLLNDIV, 0x1b);
stv0367_writereg(state, R367TER_PLLMDIV, 0xa);
stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
stv0367_writereg(state, R367TER_PLLMDIV, 0x1);
stv0367_writereg(state, R367TER_PLLNDIV, 0x8);
stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00);
stv0367_writereg(state, R367TER_DEBUG_LT5, 0x00);
stv0367_writereg(state, R367TER_DEBUG_LT6, 0x00); /* R367CAB_CTRL_1 */
stv0367_writereg(state, R367TER_DEBUG_LT7, 0x00); /* R367CAB_CTRL_2 */
stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00);
stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00);
stv0367_writereg(state, R367TER_ANADIGCTRL, 0x89);
stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */
stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
stv0367_writereg(state, R367TER_TOPCTRL, 0x00); /* Set OFDM */
stv0367_writereg(state, R367TER_ANACTRL, 0x00);
stv0367_writereg(state, R367TER_PLLMDIV, 0xc);
stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00);
stv0367_writereg(state, R367TER_DEBUG_LT5, 0x01);
stv0367_writereg(state, R367TER_DEBUG_LT6, 0x06); /* R367CAB_CTRL_1 */
stv0367_writereg(state, R367TER_DEBUG_LT7, 0x03); /* R367CAB_CTRL_2 */
stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00);
stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00);
stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8B);
stv0367_writereg(state, R367TER_DUAL_AD12, 0x04);
stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
stv0367_writereg(state, R367TER_ANACTRL, 0x00);
stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
stv0367_writereg(state, R367TER_TOPCTRL, 0x00);
stv0367_writereg(state, R367TER_GAIN_SRC1, 0x2A);
stv0367_writereg(state, R367TER_GAIN_SRC2, 0xD6);
stv0367_writereg(state, R367TER_INC_DEROT1, 0x55);
stv0367_writereg(state, R367TER_INC_DEROT2, 0x55);
stv0367_writereg(state, R367TER_TRL_CTL, 0x14);
stv0367_writereg(state, R367TER_TRL_NOMRATE1, 0xAE);
stv0367_writereg(state, R367TER_TRL_NOMRATE2, 0x56);
stv0367_writereg(state, R367TER_FEPATH_CFG, 0x0);
stv0367_writereg(state, R367TER_TSCFGH, 0x70);
stv0367_writereg(state, R367TER_TSCFGM, 0xC0);
stv0367_writereg(state, R367TER_TSCFGL, 0x20);
stv0367_writereg(state, R367TER_TSSPEED, 0x40); /* Fixed at 54 MHz */
stv0367_writereg(state, R367TER_TSCFGH, 0x71);
stv0367_writereg(state, R367TER_TSCFGH, 0x70);
stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
stv0367_writereg(state, R367TER_AGC12C, 0x01); /* AGC Pin setup */
stv0367_writereg(state, R367TER_AGCCTRL1, 0x8A);
stv0367_writereg(state, R367CAB_OUTFORMAT_0, 0x85);
stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8b);
stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */
stv0367_writereg(state, R367CAB_FSM_SNR2_HTH, 0x23);
stv0367_writereg(state, R367CAB_IQ_QAM, 0x01);
stv0367_writereg(state, R367CAB_EQU_FFE_LEAKAGE, 0x83);
stv0367_writereg(state, R367CAB_IQDEM_ADJ_EN, 0x05);
stv0367_writereg(state, R367TER_ANACTRL, 0x00);
stv0367_writereg(state, R367TER_I2CRPT, (0x08 | ((5 & 0x07) << 4)));
stv0367_writereg(state, R367TER_I2CRPT, tmp);
stv0367_writereg(state,
stv0367_writereg(state,
stv0367_writereg(state, R367TER_CHC_CTL, 0x01);
stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
stv0367_writereg(state, R367TER_SFDLYSETH, 0xc0);
stv0367_writereg(state, R367TER_SFDLYSETM, 0x60);
stv0367_writereg(state, R367TER_SFDLYSETL, 0x0);
stv0367_writereg(state, R367TER_SFDLYSETH, 0x0);
stv0367_writereg(state, R367TER_I2CRPT, 0xa0);
stv0367_writereg(state, R367TER_ANACTRL, 0x00);