stv0299_readreg
index = stv0299_readreg (state, 0x1b);
while (stv0299_readreg(state, 0x0a) & 1) {
while ((stv0299_readreg(state, 0x0a) & 3) != 2 ) {
val = stv0299_readreg (state, 0x08);
val = stv0299_readreg (state, 0x08);
val = stv0299_readreg (state, 0x08);
reg0x08 = stv0299_readreg (state, 0x08);
reg0x0c = stv0299_readreg (state, 0x0c);
reg0x08 = stv0299_readreg (state, 0x08);
reg0x0c = stv0299_readreg (state, 0x0c);
u8 signal = 0xff - stv0299_readreg (state, 0x18);
u8 sync = stv0299_readreg (state, 0x1b);
*ber = stv0299_readreg(state, 0x1e) | (stv0299_readreg(state, 0x1d) << 8);
s32 signal = 0xffff - ((stv0299_readreg (state, 0x18) << 8)
| stv0299_readreg (state, 0x19));
stv0299_readreg (state, 0x18),
stv0299_readreg (state, 0x19), (int) signal);
s32 xsnr = 0xffff - ((stv0299_readreg (state, 0x24) << 8)
| stv0299_readreg (state, 0x25));
state->ucblocks += stv0299_readreg(state, 0x1e);
state->ucblocks += (stv0299_readreg(state, 0x1d) << 8);
stv0299_writeregI(state, 0x0c, (stv0299_readreg(state, 0x0c) & 0xfe) | invval);
derot_freq = (s32)(s16) ((stv0299_readreg (state, 0x22) << 8)
| stv0299_readreg (state, 0x23));
invval = stv0299_readreg (state, 0x0c) & 1;
id = stv0299_readreg(state, 0x00);