drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

10153

static struct soc_state_bounding_box_st dml_get_soc_state_bounding_box(

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

10189

struct soc_state_bounding_box_st *state = &mode_lib->ms.state;

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core_structs.h

1268

struct soc_state_bounding_box_st state_array[__DML_MAX_STATE_ARRAY_SIZE__]; /// <brief fixed size array that holds states struct

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core_structs.h

813

struct soc_state_bounding_box_st state; //<brief Per-state bbox values; only 1 state per compute

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core_structs.h

818

struct soc_state_bounding_box_st max_state; //<brief The MAX power state; some algo needs to know the max state info to determine if

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c

635

__DML_DLL_EXPORT__ void dml_print_soc_state_bounding_box(const struct soc_state_bounding_box_st *state)

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.h

64

__DML_DLL_EXPORT__ void dml_print_soc_state_bounding_box(const struct soc_state_bounding_box_st *state);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.c

119

memset(&table->state_array[--table->num_states], 0, sizeof(struct soc_state_bounding_box_st));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.c

31

struct soc_state_bounding_box_st *entry)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.c

55

struct soc_state_bounding_box_st *entry)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.c

77

struct soc_state_bounding_box_st *entry)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.h

39

struct soc_state_bounding_box_st entry;