stm32_dma_write
stm32_dma_write(dmadev, STM32_DMA_IFCR(chan->id), dma_ifcr);
stm32_dma_write(dmadev, reg, dma_scr);
stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), dma_sfcr);
stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);
stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar);
stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar);
stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr);
stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar);
stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr);
stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);
stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), dma_sm0ar);
stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), dma_sm1ar);
stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), sg_req->chan_reg.dma_sndtr);
stm32_dma_write(dmadev, STM32_DMA_SPAR(id), sg_req->chan_reg.dma_spar);
stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), sg_req->chan_reg.dma_sm0ar);
stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), sg_req->chan_reg.dma_sm1ar);
stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
stm32_dma_write(dmadev, STM32_DMA_SPAR(id), spar + offset);
stm32_dma_write(dmadev, STM32_DMA_SPAR(id), spar);
stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), sm1ar + offset);
stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), sm0ar + offset);
stm32_dma_write(dmadev, STM32_DMA_SNDTR(id), chan_reg.dma_sndtr);
stm32_dma_write(dmadev, STM32_DMA_SCR(id), chan_reg.dma_scr);