stf_isp_reg_write
stf_isp_reg_write(stfcamss, ISP_REG_ISP_CTRL_0,
stf_isp_reg_write(stfcamss, ISP_REG_ISP_CTRL_0,
stf_isp_reg_write(stfcamss, ISP_REG_Y_PLANE_START_ADDR, y_addr);
stf_isp_reg_write(stfcamss, ISP_REG_UV_PLANE_START_ADDR, uv_addr);
stf_isp_reg_write(stfcamss, ISP_REG_LCCF_CFG_0,
stf_isp_reg_write(stfcamss, ISP_REG_LCCF_CFG_1, LCCF_MAX_DIS(0xb));
stf_isp_reg_write(stfcamss, reg_add,
stf_isp_reg_write(stfcamss, reg_add, reg_val);
stf_isp_reg_write(stfcamss, reg_add, reg_val);
stf_isp_reg_write(stfcamss, reg_add, reg_val);
stf_isp_reg_write(stfcamss, ISP_REG_ICTC,
stf_isp_reg_write(stfcamss, ISP_REG_IDBC, BADGT(0x200) | BADXT(0x200));
stf_isp_reg_write(stfcamss, ISP_REG_RAW_FORMAT_CFG,
stf_isp_reg_write(stfcamss, ISP_REG_ICFAM, CROSS_COV(3) | HV_W(2));
stf_isp_reg_write(stfcamss, ISP_REG_ICAMD_0, DNRM_F(6) | CCM_M_DAT(0));
stf_isp_reg_write(stfcamss, ISP_REG_OBC_CFG, OBC_W_H(11) | OBC_W_W(11));
stf_isp_reg_write(stfcamss, reg_add, CCM_M_DAT(0x80));
stf_isp_reg_write(stfcamss, ISP_REG_ICAMD_24, CCM_M_DAT(0x700));
stf_isp_reg_write(stfcamss, ISP_REG_ICAMD_25, CCM_M_DAT(0x200));
stf_isp_reg_write(stfcamss, ISP_REG_GAMMA_VAL0, reg_val);
stf_isp_reg_write(stfcamss, reg_add, reg_val);
stf_isp_reg_write(stfcamss, reg_add, reg_val);
stf_isp_reg_write(stfcamss, ISP_REG_GAMMA_VAL14, reg_val);
stf_isp_reg_write(stfcamss, ISP_REG_R2Y_0, 0x4C);
stf_isp_reg_write(stfcamss, ISP_REG_R2Y_1, 0x97);
stf_isp_reg_write(stfcamss, ISP_REG_R2Y_2, 0x1d);
stf_isp_reg_write(stfcamss, ISP_REG_R2Y_3, 0x1d5);
stf_isp_reg_write(stfcamss, ISP_REG_R2Y_4, 0x1ac);
stf_isp_reg_write(stfcamss, ISP_REG_R2Y_5, 0x80);
stf_isp_reg_write(stfcamss, ISP_REG_R2Y_6, 0x80);
stf_isp_reg_write(stfcamss, ISP_REG_R2Y_7, 0x194);
stf_isp_reg_write(stfcamss, ISP_REG_R2Y_8, 0x1ec);
stf_isp_reg_write(stfcamss, reg_add, reg_val);
stf_isp_reg_write(stfcamss, reg_add, y_curve);
stf_isp_reg_write(sc, ISP_REG_SHARPEN0, S_DELTA(0x7) | S_WEIGHT(0xf));
stf_isp_reg_write(sc, ISP_REG_SHARPEN1, S_DELTA(0x18) | S_WEIGHT(0xf));
stf_isp_reg_write(sc, ISP_REG_SHARPEN2, S_DELTA(0x80) | S_WEIGHT(0xf));
stf_isp_reg_write(sc, ISP_REG_SHARPEN3, S_DELTA(0x100) | S_WEIGHT(0xf));
stf_isp_reg_write(sc, ISP_REG_SHARPEN4, S_DELTA(0x10) | S_WEIGHT(0xf));
stf_isp_reg_write(sc, ISP_REG_SHARPEN5, S_DELTA(0x60) | S_WEIGHT(0xf));
stf_isp_reg_write(sc, ISP_REG_SHARPEN6, S_DELTA(0x100) | S_WEIGHT(0xf));
stf_isp_reg_write(sc, ISP_REG_SHARPEN7, S_DELTA(0x190) | S_WEIGHT(0xf));
stf_isp_reg_write(sc, ISP_REG_SHARPEN8, S_DELTA(0x0) | S_WEIGHT(0xf));
stf_isp_reg_write(sc, reg_add, S_WEIGHT(0xf));
stf_isp_reg_write(sc, reg_add, S_FACTOR(0x10) | S_SLOPE(0x0));
stf_isp_reg_write(sc, ISP_REG_SHARPEN_WN,
stf_isp_reg_write(sc, ISP_REG_IUVS1, UVDIFF2(0xC0) | UVDIFF1(0x40));
stf_isp_reg_write(sc, ISP_REG_IUVS2, UVF(0xff) | UVSLOPE(0x0));
stf_isp_reg_write(sc, ISP_REG_IUVCKS1,
stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_YSWR0, reg_val);
stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_CSWR0, reg_val);
stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_YSWR1, reg_val);
stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_CSWR1, reg_val);
stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_YDR0, reg_val);
stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_CDR0, reg_val);
stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_YDR1, reg_val);
stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_CDR1, reg_val);
stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_YDR2, reg_val);
stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_CDR2, reg_val);
stf_isp_reg_write(stfcamss, reg_add, reg_val);
stf_isp_reg_write(stfcamss, ISP_REG_CS_GAIN, CMAD(0x0) | CMAB(0x100));
stf_isp_reg_write(stfcamss, ISP_REG_CS_THRESHOLD, CMD(0x1f) | CMB(0x1));
stf_isp_reg_write(stfcamss, ISP_REG_CS_OFFSET, VOFF(0x0) | UOFF(0x0));
stf_isp_reg_write(stfcamss, ISP_REG_CS_HUE_F, SIN(0x0) | COS(0x100));
stf_isp_reg_write(stfcamss, ISP_REG_CS_SCALE, 0x8);
stf_isp_reg_write(stfcamss, ISP_REG_YADJ0, YOIR(0x401) | YIMIN(0x1));
stf_isp_reg_write(stfcamss, ISP_REG_YADJ1, YOMAX(0x3ff) | YOMIN(0x1));
stf_isp_reg_write(isp_dev->stfcamss, ISP_REG_DC_CFG_1, DC_AXI_ID(0x0));
stf_isp_reg_write(isp_dev->stfcamss, ISP_REG_DEC_CFG,
stf_isp_reg_write(isp_dev->stfcamss, ISP_REG_CSI_MODULE_CFG,
stf_isp_reg_write(isp_dev->stfcamss, ISP_REG_ISP_CTRL_1,
stf_isp_reg_write(stfcamss, ISP_REG_PIC_CAPTURE_START_CFG, val);
stf_isp_reg_write(stfcamss, ISP_REG_PIC_CAPTURE_END_CFG, val);
stf_isp_reg_write(stfcamss, ISP_REG_PIPELINE_XY_SIZE, val);
stf_isp_reg_write(stfcamss, ISP_REG_STRIDE, val);
stf_isp_reg_write(stfcamss, ISP_REG_RAW_FORMAT_CFG, val);
stf_isp_reg_write(stfcamss, reg_add, par_val);
stf_isp_reg_write(stfcamss, ISP_REG_ITIIWSR,
stf_isp_reg_write(stfcamss, ISP_REG_ITIDWLSR, 0x960);
stf_isp_reg_write(stfcamss, ISP_REG_ITIDRLSR, 0x960);
stf_isp_reg_write(stfcamss, ISP_REG_SENSOR, IMAGER_SEL(1));
stf_isp_reg_write(stfcamss, ISP_REG_IESHD, SHAD_UP_M);
stf_isp_reg_write(stfcamss, reg_add, par_val);
stf_isp_reg_write(stfcamss, reg_add, par_val);
stf_isp_reg_write(stfcamss, reg_add, par_val);
stf_isp_reg_write(stfcamss, reg_add, par_val);
stf_isp_reg_write(stfcamss, reg_add, par_val);
stf_isp_reg_write(stfcamss, reg_add, par_val);
stf_isp_reg_write(stfcamss, reg_add, par_val);
stf_isp_reg_write(stfcamss, reg_add, par_val);