stb0899_write_reg
stb0899_write_reg(state, STB0899_PDELCTRL, 0x4a);
stb0899_write_reg(state, STB0899_TSTRES, reg);
stb0899_write_reg(state, STB0899_TSTRES, reg);
stb0899_write_reg(state, STB0899_RTF, 0xf2);
stb0899_write_reg(state, STB0899_CFD, reg);
stb0899_write_reg(state, STB0899_CFD, reg);
stb0899_write_reg(state, STB0899_CFD, reg);
stb0899_write_reg(state, STB0899_TSTRES, reg);
stb0899_write_reg(state, STB0899_TSTRES, reg);
stb0899_write_reg(state, STB0899_DSTATUS2, 0x00); /* force search loop */
stb0899_write_reg(state, STB0899_CFD, reg);
stb0899_write_reg(state, STB0899_ACLC, 0x89);
stb0899_write_reg(state, STB0899_BCLC, bclc);
stb0899_write_reg(state, STB0899_ACLC, 0xc9);
stb0899_write_reg(state, STB0899_BCLC, bclc);
stb0899_write_reg(state, STB0899_ACLC, 0x89);
stb0899_write_reg(state, STB0899_BCLC, bclc);
stb0899_write_reg(state, STB0899_ACLC, 0xc8);
stb0899_write_reg(state, STB0899_BCLC, bclc);
stb0899_write_reg(state, STB0899_RTC, 0x46);
stb0899_write_reg(state, STB0899_CFD, 0xee);
stb0899_write_reg(state, STB0899_TSTRES, reg);
stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
stb0899_write_reg(state, STB0899_EQON, 0x01); /* Equalizer OFF while acquiring */
stb0899_write_reg(state, STB0899_VITSYNC, 0x19);
stb0899_write_reg(state, STB0899_RTF, 0);
stb0899_write_reg(state, STB0899_CFD, reg);
stb0899_write_reg(state, STB0899_RTC, 0x33);
stb0899_write_reg(state, STB0899_CFD, 0xf7);
stb0899_write_reg(state, STB0899_EQON, 0x41); /* Equalizer OFF while acquiring */
stb0899_write_reg(state, STB0899_VITSYNC, 0x39); /* SN to b'11 for acquisition */
stb0899_write_reg(state, STB0899_DEMAPVIT, 0x1a);
stb0899_write_reg(state, STB0899_BCLC, reg);
stb0899_write_reg(state, STB0899_DEMAPVIT, 44);
stb0899_write_reg(state, STB0899_BCLC, reg);
stb0899_write_reg(state, STB0899_DEMAPVIT, 60);
stb0899_write_reg(state, STB0899_BCLC, reg);
stb0899_write_reg(state, STB0899_DEMAPVIT, 75);
stb0899_write_reg(state, STB0899_BCLC, reg);
stb0899_write_reg(state, STB0899_DEMAPVIT, 88);
stb0899_write_reg(state, STB0899_ACLC, 0x88);
stb0899_write_reg(state, STB0899_BCLC, 0x9a);
stb0899_write_reg(state, STB0899_DEMAPVIT, 94);
stb0899_write_reg(state, STB0899_BCLC, reg);
stb0899_write_reg(state, STB0899_TSTRES, reg);
stb0899_write_reg(state, STB0899_CFD, reg);
stb0899_write_reg(state, STB0899_GPIO00CFG, 0x82);
stb0899_write_reg(state, STB0899_GPIO01CFG, 0x02);
stb0899_write_reg(state, STB0899_GPIO02CFG, 0x00);
stb0899_write_reg(state, STB0899_GPIO00CFG, 0x02);
stb0899_write_reg(state, STB0899_GPIO01CFG, 0x02);
stb0899_write_reg(state, STB0899_GPIO02CFG, 0x82);
stb0899_write_reg(state, STB0899_GPIO00CFG, 0x82);
stb0899_write_reg(state, STB0899_GPIO01CFG, 0x82);
stb0899_write_reg(state, STB0899_GPIO02CFG, 0x82);
stb0899_write_reg(state, STB0899_DISEQCOCFG, 0x66);
stb0899_write_reg(state, STB0899_ACRPRESC, reg);
stb0899_write_reg(state, STB0899_ACRDIV1, div);
stb0899_write_reg(state, STB0899_DISEQCOCFG, 0x20);
if (stb0899_write_reg(state, STB0899_I2CRPT, i2c_stat) < 0)
if (stb0899_write_reg(state, STB0899_I2CRPT, i2c_stat) < 0)
stb0899_write_reg(state, STB0899_FECM, reg);
stb0899_write_reg(state, STB0899_RSULC, 0xb1);
stb0899_write_reg(state, STB0899_TSULC, 0x40);
stb0899_write_reg(state, STB0899_RSLLC, 0x42);
stb0899_write_reg(state, STB0899_TSLPL, 0x12);
stb0899_write_reg(state, STB0899_TSTRES, reg);
stb0899_write_reg(state, STB0899_FECM, reg);
stb0899_write_reg(state, STB0899_RSULC, 0xb1);
stb0899_write_reg(state, STB0899_TSULC, 0x42);
stb0899_write_reg(state, STB0899_RSLLC, 0x40);
stb0899_write_reg(state, STB0899_TSLPL, 0x02);
stb0899_write_reg(state, STB0899_TSTRES, reg);
stb0899_write_reg(state, STB0899_FECM, reg);
stb0899_write_reg(state, STB0899_RSULC, 0xa1);
stb0899_write_reg(state, STB0899_TSULC, 0x61);
stb0899_write_reg(state, STB0899_RSLLC, 0x42);
stb0899_write_reg(state, STB0899_TSTRES, reg);
stb0899_write_reg(state, STB0899_AGCRFCFG, 0x11);
stb0899_write_reg(state, STB0899_AGCRFCFG, 0x1c);
stb0899_write_reg(state, STB0899_NCOARSE, mdiv);
stb0899_write_reg(state, postproc[ctl].gpio, 0x02);
stb0899_write_reg(state, postproc[ctl].gpio, 0x82);
stb0899_write_reg(state, postproc[ctl].gpio, 0x82);
stb0899_write_reg(state, postproc[ctl].gpio, 0x02);
stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
stb0899_write_reg(state, STB0899_DISFIFO, cmd->msg[i]);
stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
stb0899_write_reg(state, STB0899_DISFIFO, 0x00);
stb0899_write_reg(state, STB0899_DISFIFO, 0xff);
stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
stb0899_write_reg(state, STB0899_DISCNTRL1, old_state);
stb0899_write_reg(state, STB0899_DISCNTRL2, reg);
stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
stb0899_write_reg(state, STB0899_DISF22, f22_tx); /* DiSEqC Tx freq */
if ((rc = stb0899_write_reg(state, STB0899_SYNTCTRL, STB0899_SELOSCI)))
if ((rc = stb0899_write_reg(state, STB0899_STOPCLK1, 0x00)))
if ((rc = stb0899_write_reg(state, STB0899_STOPCLK2, 0x00)))
stb0899_write_reg(state, config->init_dev[i].address, config->init_dev[i].data);
stb0899_write_reg(state, config->init_s1_demod[i].address, config->init_s1_demod[i].data);
stb0899_write_reg(state, config->init_tst[i].address, config->init_tst[i].data);
extern int stb0899_write_reg(struct stb0899_state *state,