src_sel
PMU_FORMAT_ATTR(src_sel, "config:45-46");
static u32 ns_to_src(struct src_sel *s, u32 ns)
struct src_sel *s;
static u32 src_to_ns(struct src_sel *s, u8 src, u32 ns)
struct src_sel *s;
struct src_sel *s;
struct src_sel s[2];
struct src_sel s;
uint32_t src_sel;
REG_GET_2(SYMCLK32_SE_CNTL, SYMCLK32_SE3_SRC_SEL, &src_sel, SYMCLK32_SE3_EN, &en);
if (en == 1 && src_sel == symclk_32_le_inst)
uint32_t src_sel = 0;
REG_GET_2(SYMCLKA_CLOCK_ENABLE, SYMCLKA_FE_SRC_SEL, &src_sel, SYMCLKA_FE_EN, &en);
REG_GET_2(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_SRC_SEL, &src_sel, SYMCLKB_FE_EN, &en);
REG_GET_2(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_SRC_SEL, &src_sel, SYMCLKC_FE_EN, &en);
REG_GET_2(SYMCLKD_CLOCK_ENABLE, SYMCLKD_FE_SRC_SEL, &src_sel, SYMCLKD_FE_EN, &en);
REG_GET_2(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_SRC_SEL, &src_sel, SYMCLKE_FE_EN, &en);
if (en == 1 && src_sel == symclk_be_inst)
uint32_t src_sel;
src_sel = pll_info->dto_source - DTO_SOURCE_ID0;
DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel,
uint32_t src_sel;
src_sel = pll_info->dto_source - DTO_SOURCE_ID0;
DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel,
u32 src_sel[PIPES_PER_STAGE];
src_sel[i] = LM_BG_SRC_SEL_V12_RESET_VALUE;
src_sel[i] = (((pipe_type & 0x3) << 6) | ((rec_id & 0x3) << 4) | (pipe_id & 0xf));
*value |= src_sel[i] << (i * 8);
clkc_data->src_sel.reg = base + MESON_SDHC_CLKC;
clkc_data->src_sel.mask = 0x3;
clkc_data->src_sel.shift = 16;
&clkc_data->src_sel.hw);
div_parent.hw = &clkc_data->src_sel.hw;
struct clk_mux src_sel;
u8 src_sel;
u8 src_sel;
u8 src_sel, u32 freq, s32 phase_delay)
cmd->src_sel = src_sel;
u8 *src_sel, u32 *freq, u32 *src_freq)
if (src_sel)
*src_sel = cmd->src_sel;
u8 src_sel, u32 freq, s32 phase_delay);
u8 *src_sel, u32 *freq, u32 *src_freq);
u8 src_sel)
rtw89_phy_write32_mask(rtwdev, addr, mask, src_sel);
int snk_sel, src_sel = -1;
src_sel = i;
if (src_sel == -1)
RT1719_EVALMODE_MASK | (src_sel + 1));