spx5_rmw
spx5_rmw(BIT(inst), BIT(inst), sparx5, PORT_CONF_QSGMII_ENA);
spx5_rmw(PTP_TWOSTEP_CTRL_PTP_NXT_SET(1),
spx5_rmw(PTP_TWOSTEP_CTRL_PTP_NXT_SET(1),
spx5_rmw(HSIO_WRAP_DLL_CFG_DLL_RST_SET(0) |
spx5_rmw(HSIO_WRAP_DLL_CFG_DLL_RST_SET(0) |
spx5_rmw(HSIO_WRAP_RGMII_CFG_TX_CLK_CFG_SET(clk_sel) |
spx5_rmw(QSYS_CAL_CTRL_CAL_MODE_SET(10),
spx5_rmw(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_SET(671), /* 672->671 */
spx5_rmw(QSYS_CAL_CTRL_CAL_MODE_SET(8),
spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_SEL_SET(!act),
spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(1),
spx5_rmw(DSM_TAXI_CAL_CFG_CAL_IDX_SET(idx),
spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_VAL_SET(data->schedule[idx]),
spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(0),
spx5_rmw(DSM_TAXI_CAL_CFG_CAL_SWITCH_SET(1),
spx5_rmw(ANA_AC_PORT_SGE_CFG_MASK_SET(0xf0f0),
spx5_rmw(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_SET(1) |
spx5_rmw(FDMA_PORT_CTRL_INJ_STOP_SET(0), FDMA_PORT_CTRL_INJ_STOP,
spx5_rmw(0, BIT(tx->fdma.channel_id) & FDMA_CH_ACTIVATE_CH_ACTIVATE,
spx5_rmw(BIT(fdma->channel_id),
spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(1),
spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(100),
spx5_rmw(QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(1) |
spx5_rmw(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_SET(1),
spx5_rmw(HSCH_PORT_MODE_AGE_DIS_SET(1),
spx5_rmw(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_SET(1) |
spx5_rmw(FDMA_XTR_CFG_XTR_FIFO_WM_SET(31), FDMA_XTR_CFG_XTR_FIFO_WM,
spx5_rmw(FDMA_PORT_CTRL_XTR_STOP_SET(0), FDMA_PORT_CTRL_XTR_STOP,
spx5_rmw(BIT(fdma->channel_id),
spx5_rmw(0, BIT(fdma->channel_id) & FDMA_CH_ACTIVATE_CH_ACTIVATE,
spx5_rmw(0, BIT(fdma->channel_id) & FDMA_INTR_DB_ENA_INTR_DB_ENA,
spx5_rmw(FDMA_PORT_CTRL_XTR_STOP_SET(1), FDMA_PORT_CTRL_XTR_STOP,
spx5_rmw(LRN_AUTOAGE_CFG_UNIT_SIZE_SET(2) | /* 10 ms */
spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(1),
spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(0),
spx5_rmw(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(clk_div) |
spx5_rmw(HSCH_SYS_CLK_PER_100PS_SET(clk_period / 100),
spx5_rmw(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100),
spx5_rmw(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100),
spx5_rmw(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(clk_period / 100),
spx5_rmw(GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(clk_period / 100),
spx5_rmw(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET
spx5_rmw(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(pol_upd_int),
spx5_rmw(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL,
spx5_rmw(QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(1),
spx5_rmw(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(1),
return spx5_rmw(val, val, sparx5, ANA_AC_PROBE_PORT_CFG(idx));
return spx5_rmw(val, val, sparx5, ANA_AC_PROBE_PORT_CFG1(idx));
return spx5_rmw(0, val, sparx5, ANA_AC_PROBE_PORT_CFG(idx));
return spx5_rmw(0, val, sparx5, ANA_AC_PROBE_PORT_CFG1(idx));
spx5_rmw(ANA_AC_PROBE_CFG_PROBE_DIRECTION_SET(dir),
spx5_rmw(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_SET(portno),
spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(1),
spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(1),
spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(0),
spx5_rmw(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_SET(0),
spx5_rmw(ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_SET(max_pup_tokens),
spx5_rmw(ANA_AC_SDLB_THRES_THRES_SET(thres), ANA_AC_SDLB_THRES_THRES,
spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(1),
spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(stop_wm),
spx5_rmw(QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(1) |
spx5_rmw(QSYS_PAUSE_CFG_PAUSE_START_SET(pause_start) |
spx5_rmw(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_SET(0),
spx5_rmw(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(ETH_MAXLEN),
spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(1),
spx5_rmw(DEV2G5_DEV_RST_CTRL_PCS_TX_RST_SET(0),
spx5_rmw(QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(enable),
spx5_rmw(REW_TAG_CTRL_TAG_PCP_CFG_SET(mode) |
spx5_rmw(REW_PCP_MAP_DE1_PCP_DE1_SET(pcp),
spx5_rmw(REW_DEI_MAP_DE1_DEI_DE1_SET(dei),
spx5_rmw(REW_PCP_MAP_DE0_PCP_DE0_SET(pcp),
spx5_rmw(REW_DEI_MAP_DE0_DEI_DE0_SET(dei),
spx5_rmw(ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA_SET(qos->qos_enable) |
spx5_rmw(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_SET(pcp) |
spx5_rmw(ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL_SET(mode),
spx5_rmw(REW_DSCP_MAP_DSCP_UPDATE_ENA_SET(rewr),
spx5_rmw(ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_SET(dscp),
spx5_rmw(ANA_CL_QOS_CFG_DSCP_QOS_ENA_SET(qos->qos_enable) |
spx5_rmw(ANA_CL_DSCP_CFG_DSCP_QOS_VAL_SET(*(dscp + i)) |
spx5_rmw(ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_SET(1),
spx5_rmw(ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_SET(qos->default_prio) |
spx5_rmw(ANA_CL_VLAN_CTRL_PORT_PCP_SET(0) |
spx5_rmw(0,
spx5_rmw(HSCH_PORT_MODE_DEQUEUE_DIS,
spx5_rmw(QSYS_PAUSE_CFG_PAUSE_STOP_SET(0xFFF - 1),
spx5_rmw(HSCH_FLUSH_CTRL_FLUSH_PORT_SET(port->portno) |
spx5_rmw(0,
spx5_rmw(HSCH_FLUSH_CTRL_FLUSH_PORT_SET(port->portno) |
spx5_rmw(DEV25G_PCS25G_CFG_PCS25G_ENA_SET(0),
spx5_rmw(DEV2G5_PCS1G_CFG_PCS_ENA_SET(0),
spx5_rmw(BIT(inst),
spx5_rmw(PORT_CONF_USGMII_CFG_BYPASS_SCRAM_SET(1) |
spx5_rmw(DSM_MAC_CFG_HDX_BACKPREASSURE_SET(conf->duplex == DUPLEX_HALF),
spx5_rmw(DSM_RX_PAUSE_CFG_RX_PAUSE_EN_SET(fc_obey),
spx5_rmw(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_SET(fc_obey),
spx5_rmw(QSYS_PAUSE_CFG_PAUSE_STOP_SET(pause_stop),
spx5_rmw(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(sgmii),
spx5_rmw(DEV2G5_DEV_RST_CTRL_SPEED_SEL_SET(2) |
spx5_rmw(DEV25G_PCS25G_CFG_PCS25G_ENA_SET(1),
spx5_rmw(hsd ? 0 : bt_indx,
spx5_rmw(hsd ? 0 : bt_indx,
spx5_rmw(hsd ? 0 : bt_indx,
spx5_rmw(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_SET(gig_mode) |
spx5_rmw(HSCH_PORT_MODE_AGE_DIS_SET(fdx == 0),
spx5_rmw(DEV2G5_DEV_RST_CTRL_SPEED_SEL_SET(clk_spd) |
spx5_rmw(DEV2G5_PHAD_CTRL_DIV_CFG_SET(3) |
spx5_rmw(ASM_PORT_CFG_CSC_STAT_DIS_SET(high_speed_dev),
spx5_rmw(DSM_BUF_CFG_CSC_STAT_DIS_SET(high_speed_dev),
spx5_rmw(ANA_AC_TSN_SF_CFG_TSN_SGID_SET(sf->sgid) |
spx5_rmw(ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_SET(base_msb) |
spx5_rmw(ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_SET(1),
spx5_rmw(ANA_L2_TSN_CFG_TSN_SFID_SET(sfid), ANA_L2_TSN_CFG_TSN_SFID,
spx5_rmw(ANA_L2_DLB_CFG_DLB_IDX_SET(fmid), ANA_L2_DLB_CFG_DLB_IDX,
spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_SAVE) |
spx5_rmw(REW_PTP_TWOSTEP_CTRL_PTP_NXT_SET(1),
spx5_rmw(REW_PTP_TWOSTEP_CTRL_PTP_NXT_SET(1),
spx5_rmw(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(1 << BIT(phc->index)),
spx5_rmw(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(0),
spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_IDLE) |
spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_LOAD) |
spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_SAVE) |
spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_IDLE) |
spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_DELTA) |
spx5_rmw(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(0x7),
spx5_rmw(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(0),
spx5_rmw(HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(layer),
spx5_rmw(HSCH_HSCH_LEAK_CFG_LEAK_FIRST_SET(se_first),
spx5_rmw(HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(layer),
spx5_rmw(HSCH_SE_CFG_SE_FRM_MODE_SET(sh->mode), HSCH_SE_CFG_SE_FRM_MODE,
spx5_rmw(HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(layer) |
spx5_rmw(HSCH_SE_CFG_SE_DWRR_CNT_SET(dwrr->count),
spx5_rmw(HSCH_DWRR_ENTRY_DWRR_COST_SET(dwrr->cost[i]),
spx5_rmw(ANA_AC_SDLB_PUP_CTRL_PUP_ENA_SET(0),
spx5_rmw(ANA_AC_SDLB_PUP_CTRL_PUP_ENA_SET(1),
spx5_rmw(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(enable),
spx5_rmw(ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_SET(value),
spx5_rmw(ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL_SET(value),
spx5_rmw(ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL_SET(value),
spx5_rmw(ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_SET(value),
spx5_rmw(ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_SET(value),
spx5_rmw(ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_SET(value),
spx5_rmw(ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_SET(value),
spx5_rmw(ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_SET(value),
spx5_rmw(ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_SET(value),
spx5_rmw(EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL_SET(value),
spx5_rmw(EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL_SET(value),
spx5_rmw(EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL_SET(value),
spx5_rmw(ANA_CL_ADV_CL_CFG_LOOKUP_ENA,
spx5_rmw(ANA_ACL_VCAP_S2_CFG_SEC_ENA_SET(0xf),
spx5_rmw(keysel, REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA,
spx5_rmw(REW_ES0_CTRL_ES0_LU_ENA_SET(1), REW_ES0_CTRL_ES0_LU_ENA,
spx5_rmw(ANA_CL_ADV_CL_CFG_LOOKUP_ENA_SET(0),
spx5_rmw(ANA_ACL_VCAP_S2_CFG_SEC_ENA_SET(0),
spx5_rmw(REW_ES0_CTRL_ES0_LU_ENA_SET(0),
spx5_rmw(EACL_VCAP_ES2_KEY_SEL_KEY_ENA_SET(0),
spx5_rmw(val, mask, sparx5, ANA_AC_PGID_CFG(pgid));
spx5_rmw(val, mask, sparx5, ANA_AC_PGID_CFG1(pgid));
spx5_rmw(val, mask, sparx5, ANA_AC_PGID_CFG2(pgid));
spx5_rmw(REW_PORT_VLAN_CFG_PORT_VID_SET(port->vid),
spx5_rmw(ANA_L3_VLAN_CTRL_VLAN_ENA_SET(1),
spx5_rmw(ANA_L3_VLAN_CFG_VLAN_FID_SET(vid),
spx5_rmw(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(0) |