arch/powerpc/platforms/cell/spu_base.c

578

spu_mfc_sr1_set(spu, 0x33);

arch/powerpc/platforms/cell/spu_base.c

700

spu_mfc_sr1_set(spu, tmp);

arch/powerpc/platforms/cell/spufs/hw_ops.c

232

spu_mfc_sr1_set(spu, sr1);

arch/powerpc/platforms/cell/spufs/hw_ops.c

243

spu_mfc_sr1_set(spu, sr1);

arch/powerpc/platforms/cell/spufs/run.c

127

spu_mfc_sr1_set(ctx->spu, sr1);

arch/powerpc/platforms/cell/spufs/run.c

170

spu_mfc_sr1_set(ctx->spu, sr1);

arch/powerpc/platforms/cell/spufs/switch.c

1042

spu_mfc_sr1_set(spu,

arch/powerpc/platforms/cell/spufs/switch.c

1054

spu_mfc_sr1_set(spu,

arch/powerpc/platforms/cell/spufs/switch.c

1692

spu_mfc_sr1_set(spu, csa->priv1.mfc_sr1_RW);

arch/powerpc/platforms/cell/spufs/switch.c

1882

spu_mfc_sr1_set(spu, MFC_STATE1_MASTER_RUN_CONTROL_MASK);

arch/powerpc/platforms/cell/spufs/switch.c

496

spu_mfc_sr1_set(spu, (MFC_STATE1_MASTER_RUN_CONTROL_MASK |