spireg_write
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);
spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val);
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0);
spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 0);
spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, ~0U);
spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, cause);
spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG,
spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, 0);
spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, 0);
spireg_write(a3700_spi, A3700_SPI_IF_RMODE_REG, 0);
spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0);
spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val);
spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val);
spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, cpu_to_le32(val));
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, 0);
spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG,
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val);