drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h

227

int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1598

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1911

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2126

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2128

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2609

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_min);

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2614

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_max);

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1509

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1824

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2089

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2091

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1021

ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);