smu_registers
writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
writel(0xFF000000, &ihost->smu_registers->interrupt_mask);
writel(0, &ihost->smu_registers->interrupt_mask);
&ihost->smu_registers->interrupt_coalesce_control);
&ihost->smu_registers->interrupt_coalesce_control);
val = readl(&ihost->smu_registers->clock_gating_control);
writel(val, &ihost->smu_registers->clock_gating_control);
writel(0xFFFFFFFF, &ihost->smu_registers->soft_reset_control);
writel(0x00000000, &ihost->smu_registers->completion_queue_get);
writel(~SMU_INTERRUPT_STATUS_RESERVED_MASK, &ihost->smu_registers->interrupt_status);
ihost->smu_registers = smu_base;
writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
writel(0xFF000000, &ihost->smu_registers->interrupt_mask);
writel(0, &ihost->smu_registers->interrupt_mask);
writel(0, &ihost->smu_registers->soft_reset_control);
status = readl(&ihost->smu_registers->control_status);
val = readl(&ihost->smu_registers->device_context_capacity);
writel(lower_32_bits(ihost->cq_dma), &ihost->smu_registers->completion_queue_lower);
writel(upper_32_bits(ihost->cq_dma), &ihost->smu_registers->completion_queue_upper);
writel(lower_32_bits(ihost->rnc_dma), &ihost->smu_registers->remote_node_context_lower);
writel(upper_32_bits(ihost->rnc_dma), &ihost->smu_registers->remote_node_context_upper);
writel(lower_32_bits(ihost->tc_dma), &ihost->smu_registers->host_task_table_lower);
writel(upper_32_bits(ihost->tc_dma), &ihost->smu_registers->host_task_table_upper);
readl(&ihost->smu_registers->interrupt_status);
writel(request, &ihost->smu_registers->post_context_port);
writel(0xff, &ihost->smu_registers->interrupt_mask);
writel(0, &ihost->smu_registers->interrupt_mask);
&ihost->smu_registers->completion_queue_get);
readl(&ihost->smu_registers->interrupt_status);
writel(SMU_ISR_QUEUE_SUSPEND, &ihost->smu_registers->interrupt_status);
writel(0, &ihost->smu_registers->interrupt_mask);
writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
writel(0, &ihost->smu_registers->interrupt_mask);
writel(0xffffffff, &ihost->smu_registers->interrupt_mask);
readl(&ihost->smu_registers->interrupt_mask); /* flush */
readl(&ihost->smu_registers->task_context_assignment[0]);
&ihost->smu_registers->task_context_assignment[0]);
&ihost->smu_registers->completion_queue_control);
&ihost->smu_registers->completion_queue_get);
&ihost->smu_registers->completion_queue_put);
struct smu_registers __iomem *smu_registers;
readl(&ihost->smu_registers->interrupt_status); /* flush */
readl(&ihost->smu_registers->interrupt_status); /* flush */
if (readl(&ihost->smu_registers->address_modifier) == 0) {