drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

663

struct smu_dpm_clks *smu_dpm_clks)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

665

struct vg_dpm_clocks *table = smu_dpm_clks->dpm_clks;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

670

if (!table || smu_dpm_clks->mc_address.quad_part == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

676

smu_dpm_clks->mc_address.high_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

678

smu_dpm_clks->mc_address.low_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

688

struct smu_dpm_clks smu_dpm_clks = { 0 };

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

716

smu_dpm_clks.dpm_clks = (struct vg_dpm_clocks *)dm_helpers_allocate_gpu_mem(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

720

&smu_dpm_clks.mc_address.quad_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

722

if (smu_dpm_clks.dpm_clks == NULL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

723

smu_dpm_clks.dpm_clks = &dummy_clocks;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

724

smu_dpm_clks.mc_address.quad_part = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

727

ASSERT(smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

755

vg_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

760

smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

763

if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

765

smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

507

struct dcn31_smu_dpm_clks *smu_dpm_clks)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

509

DpmClocks_t *table = smu_dpm_clks->dpm_clks;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

514

if (!table || smu_dpm_clks->mc_address.quad_part == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

520

smu_dpm_clks->mc_address.high_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

522

smu_dpm_clks->mc_address.low_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

686

struct dcn31_smu_dpm_clks smu_dpm_clks = { 0 };

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

714

smu_dpm_clks.dpm_clks = (DpmClocks_t *)dm_helpers_allocate_gpu_mem(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

718

&smu_dpm_clks.mc_address.quad_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

720

if (smu_dpm_clks.dpm_clks == NULL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

721

smu_dpm_clks.dpm_clks = &dummy_clocks;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

722

smu_dpm_clks.mc_address.quad_part = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

725

ASSERT(smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

756

dcn31_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

765

smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

766

smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

767

smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

768

smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

769

smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

770

smu_dpm_clks.dpm_clks->MinGfxClk,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

771

smu_dpm_clks.dpm_clks->MaxGfxClk);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

772

for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

775

smu_dpm_clks.dpm_clks->DcfClocks[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

777

for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

779

i, smu_dpm_clks.dpm_clks->DispClocks[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

781

for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

783

i, smu_dpm_clks.dpm_clks->SocClocks[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

787

i, smu_dpm_clks.dpm_clks->SocVoltage[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

793

i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

794

i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

795

i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

801

smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

805

if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

807

smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

578

struct dcn314_smu_dpm_clks *smu_dpm_clks)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

580

DpmClocks314_t *table = smu_dpm_clks->dpm_clks;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

585

if (!table || smu_dpm_clks->mc_address.quad_part == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

591

smu_dpm_clks->mc_address.high_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

593

smu_dpm_clks->mc_address.low_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

803

struct dcn314_smu_dpm_clks smu_dpm_clks = { 0 };

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

831

smu_dpm_clks.dpm_clks = (DpmClocks314_t *)dm_helpers_allocate_gpu_mem(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

835

&smu_dpm_clks.mc_address.quad_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

837

if (smu_dpm_clks.dpm_clks == NULL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

838

smu_dpm_clks.dpm_clks = &dummy_clocks;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

839

smu_dpm_clks.mc_address.quad_part = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

842

ASSERT(smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

873

dcn314_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

881

smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

882

smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

883

smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

884

smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

885

smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

886

smu_dpm_clks.dpm_clks->MinGfxClk,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

887

smu_dpm_clks.dpm_clks->MaxGfxClk);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

888

for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

891

smu_dpm_clks.dpm_clks->DcfClocks[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

893

for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

895

i, smu_dpm_clks.dpm_clks->DispClocks[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

897

for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

899

i, smu_dpm_clks.dpm_clks->SocClocks[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

903

i, smu_dpm_clks.dpm_clks->SocVoltage[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

909

i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

910

i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

911

i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

918

smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

922

if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

924

smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

470

struct dcn315_smu_dpm_clks *smu_dpm_clks)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

472

DpmClocks_315_t *table = smu_dpm_clks->dpm_clks;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

477

if (!table || smu_dpm_clks->mc_address.quad_part == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

483

smu_dpm_clks->mc_address.high_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

485

smu_dpm_clks->mc_address.low_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

619

struct dcn315_smu_dpm_clks smu_dpm_clks = { 0 };

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

647

smu_dpm_clks.dpm_clks = (DpmClocks_315_t *)dm_helpers_allocate_gpu_mem(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

651

&smu_dpm_clks.mc_address.quad_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

653

if (smu_dpm_clks.dpm_clks == NULL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

654

smu_dpm_clks.dpm_clks = &dummy_clocks;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

655

smu_dpm_clks.mc_address.quad_part = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

658

ASSERT(smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

686

dcn315_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

694

smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

695

smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

696

smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

697

smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

698

smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

699

smu_dpm_clks.dpm_clks->MinGfxClk,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

700

smu_dpm_clks.dpm_clks->MaxGfxClk);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

701

for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

704

smu_dpm_clks.dpm_clks->DcfClocks[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

706

for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

708

i, smu_dpm_clks.dpm_clks->DispClocks[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

710

for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

712

i, smu_dpm_clks.dpm_clks->SocClocks[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

716

i, smu_dpm_clks.dpm_clks->SocVoltage[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

722

i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

723

i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

724

i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

731

smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

735

if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

737

smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

436

struct dcn316_smu_dpm_clks *smu_dpm_clks)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

438

DpmClocks_316_t *table = smu_dpm_clks->dpm_clks;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

443

if (!table || smu_dpm_clks->mc_address.quad_part == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

449

smu_dpm_clks->mc_address.high_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

451

smu_dpm_clks->mc_address.low_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

594

struct dcn316_smu_dpm_clks smu_dpm_clks = { 0 };

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

622

smu_dpm_clks.dpm_clks = (DpmClocks_316_t *)dm_helpers_allocate_gpu_mem(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

626

&smu_dpm_clks.mc_address.quad_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

628

if (smu_dpm_clks.dpm_clks == NULL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

629

smu_dpm_clks.dpm_clks = &dummy_clocks;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

630

smu_dpm_clks.mc_address.quad_part = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

633

ASSERT(smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

669

dcn316_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

675

smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

679

if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

681

smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1426

struct dcn35_smu_dpm_clks smu_dpm_clks = { 0 };

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1459

smu_dpm_clks.dpm_clks = (DpmClocks_t_dcn35 *)dm_helpers_allocate_gpu_mem(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1463

&smu_dpm_clks.mc_address.quad_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1464

if (smu_dpm_clks.dpm_clks == NULL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1465

smu_dpm_clks.dpm_clks = &dummy_clocks;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1466

smu_dpm_clks.mc_address.quad_part = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1468

ASSERT(smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1513

translate_to_DpmClocks_t_dcn35(&smu_dpm_clks_dcn351, &smu_dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1515

dcn35_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1524

smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1525

smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1526

smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1527

smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1528

smu_dpm_clks.dpm_clks->NumFclkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1529

smu_dpm_clks.dpm_clks->NumMemPstatesEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1530

smu_dpm_clks.dpm_clks->MinGfxClk,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1531

smu_dpm_clks.dpm_clks->MaxGfxClk);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1532

for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1535

smu_dpm_clks.dpm_clks->DcfClocks[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1537

for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1539

i, smu_dpm_clks.dpm_clks->DispClocks[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1541

for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1543

i, smu_dpm_clks.dpm_clks->SocClocks[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1545

for (i = 0; i < smu_dpm_clks.dpm_clks->NumFclkLevelsEnabled; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1547

i, smu_dpm_clks.dpm_clks->FclkClocks_Freq[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1549

i, smu_dpm_clks.dpm_clks->FclkClocks_Voltage[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1551

for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1553

i, smu_dpm_clks.dpm_clks->SocVoltage[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1555

for (i = 0; i < smu_dpm_clks.dpm_clks->NumMemPstatesEnabled; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1559

i, smu_dpm_clks.dpm_clks->MemPstateTable[i].UClk,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1560

i, smu_dpm_clks.dpm_clks->MemPstateTable[i].MemClk,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1561

i, smu_dpm_clks.dpm_clks->MemPstateTable[i].Voltage);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1568

smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1572

if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1574

smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

964

struct dcn35_smu_dpm_clks *smu_dpm_clks)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

966

DpmClocks_t_dcn35 *table = smu_dpm_clks->dpm_clks;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

971

if (!table || smu_dpm_clks->mc_address.quad_part == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

977

smu_dpm_clks->mc_address.high_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

979

smu_dpm_clks->mc_address.low_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

984

struct dcn351_smu_dpm_clks *smu_dpm_clks)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

986

DpmClocks_t_dcn351 *table = smu_dpm_clks->dpm_clks;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

990

if (!table || smu_dpm_clks->mc_address.quad_part == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

994

smu_dpm_clks->mc_address.high_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

996

smu_dpm_clks->mc_address.low_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1017

if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1019

smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

534

struct dcn42_smu_dpm_clks *smu_dpm_clks)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

536

DpmClocks_t_dcn42 *table = smu_dpm_clks->dpm_clks;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

541

if (!table || smu_dpm_clks->mc_address.quad_part == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

547

smu_dpm_clks->mc_address.high_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

549

smu_dpm_clks->mc_address.low_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

904

struct dcn42_smu_dpm_clks smu_dpm_clks = { 0 };

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

909

smu_dpm_clks.dpm_clks = (DpmClocks_t_dcn42 *)dm_helpers_allocate_gpu_mem(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

913

&smu_dpm_clks.mc_address.quad_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

915

ASSERT(smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

916

if (clk_mgr_base->ctx->dc->debug.pstate_enabled && smu_dpm_clks.mc_address.quad_part != 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

918

DpmClocks_t_dcn42 *dpm_clks = smu_dpm_clks.dpm_clks;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

920

dcn42_get_dpm_table_from_smu(clk_mgr_int, &smu_dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

82

void dcn42_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr, struct dcn42_smu_dpm_clks *smu_dpm_clks);