CS42L42_PWR_CTL2
{ CS42L42_PWR_CTL2, 0x84 },
{ CS42L42_PWR_CTL2, 0x84 },
{ CS42L42_PWR_CTL2, 0x84 },
cs8409_i2c_write(cs42l42, CS42L42_PWR_CTL2, 0x87);
{ CS42L42_PWR_CTL2, 0x8C },
cs8409_i2c_write(cs42l42, CS42L42_PWR_CTL2, 0x9C);
case CS42L42_PWR_CTL2:
REG_SEQ0(CS42L42_PWR_CTL2, 0x8C),
regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL2,
regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL2,
SND_SOC_DAPM_PGA("DACSRC", CS42L42_PWR_CTL2, CS42L42_DAC_SRC_PDNB_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ADCSRC", CS42L42_PWR_CTL2, CS42L42_ADC_SRC_PDNB_SHIFT, 0, NULL, 0),
{ CS42L42_PWR_CTL2, 0x84 },
{ CS42L42_PWR_CTL2, 0x84 },