soc_v1_0_normalize_xcc_reg_offset
addr0 = soc_v1_0_normalize_xcc_reg_offset(addr0);
addr1 = soc_v1_0_normalize_xcc_reg_offset(addr1);
reg = soc_v1_0_normalize_xcc_reg_offset(reg);
reg = soc_v1_0_normalize_xcc_reg_offset(reg);
uint32_t normalized_reg = soc_v1_0_normalize_xcc_reg_offset(reg);
soc_v1_0_normalize_xcc_reg_offset(misc_pkt.read_reg.reg_offset);
soc_v1_0_normalize_xcc_reg_offset(misc_pkt.write_reg.reg_offset);
soc_v1_0_normalize_xcc_reg_offset(misc_pkt.wait_reg_mem.reg_offset1);
soc_v1_0_normalize_xcc_reg_offset(misc_pkt.wait_reg_mem.reg_offset1);
soc_v1_0_normalize_xcc_reg_offset(misc_pkt.wait_reg_mem.reg_offset2);
amdgpu_ring_write(ring, soc_v1_0_normalize_xcc_reg_offset(reg) << 2);
amdgpu_ring_write(ring, soc_v1_0_normalize_xcc_reg_offset(reg) << 2);
uint32_t soc_v1_0_normalize_xcc_reg_offset(uint32_t reg);