CS42L42_ASP_CLK_CFG
{ CS42L42_ASP_CLK_CFG, 0x20 },
{ CS42L42_ASP_CLK_CFG, 0x20 },
{ CS42L42_ASP_CLK_CFG, 0x20 },
{ CS42L42_ASP_CLK_CFG, 0x00 },
case CS42L42_ASP_CLK_CFG:
REG_SEQ0(CS42L42_ASP_CLK_CFG, 0x00),
SND_SOC_DAPM_SUPPLY("SCLK", CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0),
{ CS42L42_ASP_CLK_CFG, 0x00 },
snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK |
{ CS42L42_ASP_CLK_CFG, 0x00 },