sky2_read16
reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
(unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
status = sky2_read16(hw, HCU_CCSR);
reg = sky2_read16(hw, GPHY_CTRL);
reg = sky2_read16(hw, Y2_CFG_SPC + PCI_LDO_CTRL);
ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
last = sky2_read16(hw, STAT_PUT_IDX);
sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
return sky2_read16(hw, SK_GMAC_REG(port,reg));
return (u32) sky2_read16(hw, base)
| (u32) sky2_read16(hw, base+4) << 16;
return (u64) sky2_read16(hw, base)
| (u64) sky2_read16(hw, base+4) << 16
| (u64) sky2_read16(hw, base+8) << 32
| (u64) sky2_read16(hw, base+12) << 48;
return sky2_read16(hw, Y2_CFG_SPC + reg);