Symbol: skl_ddb_entry
drivers/gpu/drm/i915/display/intel_cursor.c
593
static u32 skl_cursor_ddb_reg_val(const struct skl_ddb_entry *entry)
drivers/gpu/drm/i915/display/intel_cursor.c
624
const struct skl_ddb_entry *ddb =
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
100
const struct skl_ddb_entry *ddb,
drivers/gpu/drm/i915/display/intel_display.c
7004
struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
drivers/gpu/drm/i915/display/intel_display_debugfs.c
663
struct skl_ddb_entry *entry;
drivers/gpu/drm/i915/display/intel_display_types.h
928
struct skl_ddb_entry ddb;
drivers/gpu/drm/i915/display/intel_display_types.h
933
struct skl_ddb_entry plane_ddb[I915_MAX_PLANES];
drivers/gpu/drm/i915/display/intel_display_types.h
935
struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
drivers/gpu/drm/i915/display/intel_plane.c
1020
struct skl_ddb_entry ddb[I915_MAX_PLANES];
drivers/gpu/drm/i915/display/intel_plane.c
1021
struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
drivers/gpu/drm/i915/display/intel_plane.c
888
struct skl_ddb_entry ddb[I915_MAX_PLANES],
drivers/gpu/drm/i915/display/intel_plane.c
889
struct skl_ddb_entry ddb_y[I915_MAX_PLANES],
drivers/gpu/drm/i915/display/intel_wm_types.h
62
static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
drivers/gpu/drm/i915/display/intel_wm_types.h
67
static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
drivers/gpu/drm/i915/display/intel_wm_types.h
68
const struct skl_ddb_entry *e2)
drivers/gpu/drm/i915/display/skl_universal_plane.c
779
static u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
drivers/gpu/drm/i915/display/skl_universal_plane.c
829
const struct skl_ddb_entry *ddb =
drivers/gpu/drm/i915/display/skl_universal_plane.c
831
const struct skl_ddb_entry *ddb_y =
drivers/gpu/drm/i915/display/skl_universal_plane.h
15
struct skl_ddb_entry;
drivers/gpu/drm/i915/display/skl_watermark.c
1349
skl_check_wm_level(struct skl_wm_level *wm, const struct skl_ddb_entry *ddb)
drivers/gpu/drm/i915/display/skl_watermark.c
1357
const struct skl_ddb_entry *ddb_y,
drivers/gpu/drm/i915/display/skl_watermark.c
1358
const struct skl_ddb_entry *ddb)
drivers/gpu/drm/i915/display/skl_watermark.c
1391
struct skl_ddb_entry *ddb, u64 data_rate)
drivers/gpu/drm/i915/display/skl_watermark.c
1417
struct skl_ddb_entry *ddb, u64 data_rate)
drivers/gpu/drm/i915/display/skl_watermark.c
1425
struct skl_ddb_entry *ddb_y, u64 data_rate_y,
drivers/gpu/drm/i915/display/skl_watermark.c
1426
struct skl_ddb_entry *ddb, u64 data_rate)
drivers/gpu/drm/i915/display/skl_watermark.c
1440
const struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe];
drivers/gpu/drm/i915/display/skl_watermark.c
1484
const struct skl_ddb_entry *ddb =
drivers/gpu/drm/i915/display/skl_watermark.c
1524
struct skl_ddb_entry *ddb =
drivers/gpu/drm/i915/display/skl_watermark.c
1526
struct skl_ddb_entry *ddb_y =
drivers/gpu/drm/i915/display/skl_watermark.c
1561
const struct skl_ddb_entry *ddb =
drivers/gpu/drm/i915/display/skl_watermark.c
1563
const struct skl_ddb_entry *ddb_y =
drivers/gpu/drm/i915/display/skl_watermark.c
1587
const struct skl_ddb_entry *ddb =
drivers/gpu/drm/i915/display/skl_watermark.c
1589
const struct skl_ddb_entry *ddb_y =
drivers/gpu/drm/i915/display/skl_watermark.c
2400
static bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
drivers/gpu/drm/i915/display/skl_watermark.c
2401
const struct skl_ddb_entry *b)
drivers/gpu/drm/i915/display/skl_watermark.c
2406
static void skl_ddb_entry_union(struct skl_ddb_entry *a,
drivers/gpu/drm/i915/display/skl_watermark.c
2407
const struct skl_ddb_entry *b)
drivers/gpu/drm/i915/display/skl_watermark.c
2418
bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
drivers/gpu/drm/i915/display/skl_watermark.c
2419
const struct skl_ddb_entry *entries,
drivers/gpu/drm/i915/display/skl_watermark.c
2603
const struct skl_ddb_entry *old,
drivers/gpu/drm/i915/display/skl_watermark.c
2604
const struct skl_ddb_entry *new,
drivers/gpu/drm/i915/display/skl_watermark.c
2702
const struct skl_ddb_entry *old, *new;
drivers/gpu/drm/i915/display/skl_watermark.c
3053
struct skl_ddb_entry *ddb =
drivers/gpu/drm/i915/display/skl_watermark.c
3055
struct skl_ddb_entry *ddb_y =
drivers/gpu/drm/i915/display/skl_watermark.c
3756
struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
drivers/gpu/drm/i915/display/skl_watermark.c
3889
const struct skl_ddb_entry *hw_ddb_entry,
drivers/gpu/drm/i915/display/skl_watermark.c
3890
const struct skl_ddb_entry *sw_ddb_entry)
drivers/gpu/drm/i915/display/skl_watermark.c
3911
struct skl_ddb_entry ddb[I915_MAX_PLANES];
drivers/gpu/drm/i915/display/skl_watermark.c
3912
struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
drivers/gpu/drm/i915/display/skl_watermark.c
394
static u16 skl_ddb_entry_init(struct skl_ddb_entry *entry,
drivers/gpu/drm/i915/display/skl_watermark.c
411
struct skl_ddb_entry *ddb)
drivers/gpu/drm/i915/display/skl_watermark.c
43
struct skl_ddb_entry ddb[I915_MAX_PIPES];
drivers/gpu/drm/i915/display/skl_watermark.c
430
struct skl_ddb_entry ddb;
drivers/gpu/drm/i915/display/skl_watermark.c
443
const struct skl_ddb_entry *entry)
drivers/gpu/drm/i915/display/skl_watermark.c
531
struct skl_ddb_entry ddb_slices;
drivers/gpu/drm/i915/display/skl_watermark.c
666
static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
drivers/gpu/drm/i915/display/skl_watermark.c
679
struct skl_ddb_entry *ddb,
drivers/gpu/drm/i915/display/skl_watermark.c
680
struct skl_ddb_entry *ddb_y,
drivers/gpu/drm/i915/display/skl_watermark.c
710
struct skl_ddb_entry *ddb,
drivers/gpu/drm/i915/display/skl_watermark.c
711
struct skl_ddb_entry *ddb_y,
drivers/gpu/drm/i915/display/skl_watermark.h
19
struct skl_ddb_entry;
drivers/gpu/drm/i915/display/skl_watermark.h
31
const struct skl_ddb_entry *entry);
drivers/gpu/drm/i915/display/skl_watermark.h
33
bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
drivers/gpu/drm/i915/display/skl_watermark.h
34
const struct skl_ddb_entry *entries,