snd_sof_dsp_update_bits_unlocked
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2,
snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL0,
snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_PMCS,
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CLKCTL,
snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2,
snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2,
snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL0,
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR2,
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IPCD,
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IMRX,
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IPCX,
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IMRX,
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS,
EXPORT_SYMBOL(snd_sof_dsp_update_bits_unlocked);
return snd_sof_dsp_update_bits_unlocked(sdev, bar, offset, mask, value);
bool snd_sof_dsp_update_bits_unlocked(struct snd_sof_dev *sdev, u32 bar,