sifive_spi_write
sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
sifive_spi_write(spi, SIFIVE_SPI_REG_TXMARK, 1);
sifive_spi_write(spi, SIFIVE_SPI_REG_RXMARK, 0);
sifive_spi_write(spi, SIFIVE_SPI_REG_DELAY0,
sifive_spi_write(spi, SIFIVE_SPI_REG_DELAY1,
sifive_spi_write(spi, SIFIVE_SPI_REG_FCTRL, 0);
sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);
sifive_spi_write(spi, SIFIVE_SPI_REG_CSID, spi_get_chipselect(device, 0));
sifive_spi_write(spi, SIFIVE_SPI_REG_SCKMODE,
sifive_spi_write(spi, SIFIVE_SPI_REG_CSMODE, is_high ?
sifive_spi_write(spi, SIFIVE_SPI_REG_SCKDIV, cr);
sifive_spi_write(spi, SIFIVE_SPI_REG_FMT, cr);
sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
sifive_spi_write(spi, SIFIVE_SPI_REG_IE, bit);
sifive_spi_write(spi, SIFIVE_SPI_REG_TXDATA,
sifive_spi_write(spi, SIFIVE_SPI_REG_RXMARK,
sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, 0xffffffffU);
sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);
sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);