snd_hdac_chip_readl
(snd_hdac_chip_readl(chip, reg) & ~(mask)) | (val))
if (snd_hdac_chip_readl(azx_bus(chip), GTSCC) &
wallclk_ctr = snd_hdac_chip_readl(azx_bus(chip), WALFCC);
tsc_counter_l = snd_hdac_chip_readl(azx_bus(chip), TSCCL);
tsc_counter_h = snd_hdac_chip_readl(azx_bus(chip), TSCCU);
ll_counter_l = snd_hdac_chip_readl(azx_bus(chip), LLPCL);
ll_counter_h = snd_hdac_chip_readl(azx_bus(chip), LLPCU);
snd_hdac_chip_readl(azx_bus(chip), reg)
bus->rirb.res[addr] = snd_hdac_chip_readl(bus, IR);
azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))
return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO;
status = snd_hdac_chip_readl(bus, INTSTS);
intsts = snd_hdac_chip_readl(bus, INTSTS);
status = snd_hdac_chip_readl(bus, INTSTS);