drivers/gpu/drm/amd/pm/swsmu/inc/smu_v12_0.h

58

int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1473

.set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

701

ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq, false);

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

734

ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false);

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

888

ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq, false);

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

896

ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq, false);

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

938

ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk, sclk, false);

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

941

ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk, socclk, false);

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

944

ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_FCLK, fclk, fclk, false);