drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h

241

int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1594

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1907

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2122

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2124

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2605

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_min);

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2610

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_max);

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1508

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1823

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2088

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2090

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1096

ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);