drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

108

smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

116

smu_print("SMU Test message: %d\n", input);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

128

smu_print("SMU Get SMU version\n");

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

133

smu_print("SMU version: %d\n", *version);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

146

smu_print("SMU Check driver if version\n");

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

151

smu_print("SMU driver if version: %d\n", response);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

165

smu_print("SMU Check msg header version\n");

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

170

smu_print("SMU msg header version: %d\n", response);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

181

smu_print("SMU Set DRAM addr high: %d\n", addr_high);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

189

smu_print("SMU Set DRAM addr low: %d\n", addr_low);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

197

smu_print("SMU Transfer WM table SMU 2 DRAM\n");

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

205

smu_print("SMU Transfer WM table DRAM 2 SMU\n");

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

219

smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

224

smu_print("SMU Frequency set = %d MHz\n", response);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

237

smu_print("SMU Set hard max by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

242

smu_print("SMU Frequency set = %d MHz\n", response);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

268

smu_print("SMU Get dpm freq by index: clk = %d, dpm_level = %d\n", clk, dpm_level);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

273

smu_print("SMU dpm freq: %d MHz\n", response);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

286

smu_print("SMU Get DC mode max DPM freq: clk = %d\n", clk);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

291

smu_print("SMU DC mode max DMP freq: %d MHz\n", response);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

298

smu_print("SMU Set min deep sleep dcef clk: freq_mhz = %d MHz\n", freq_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

306

smu_print("SMU Set num of displays: num_displays = %d\n", num_displays);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

317

smu_print("SMU Set display refresh from mall: enable = %d, cache_timer_delay = %d, cache_timer_scale = %d\n",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

326

smu_print("SMU Set external client df cstate allow: enable = %d\n", enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

334

smu_print("SMU Set PME workaround\n");

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c

112

smu_print("SMU Set SmartMux Switch: switch_dgpu = %d\n", pins_to_set);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

107

smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

112

smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

128

smu_print("SMU Response was not OK. SMU response after wait received is: %d\n",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

143

smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

164

smu_print("SMU msg id write fail %x times. \n", i + 1);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

127

smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

163

smu_print("FCLK P-state support value is : %d\n", enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

174

smu_print("Numways for SubVP : %d\n", num_ways);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

179

smu_print("SMU Transfer WM table DRAM 2 SMU\n");

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

187

smu_print("SMU Set PME workaround\n");

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

220

smu_print("SMU Get hard min status: no_timeout %d delay %d us clk bits %x\n",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

264

smu_print("SMU Wait get hard min status: %d timeouts\n", cur_wait_get_hard_min_max_timeouts);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

274

smu_print("SMU Wait get hard min status: no_timeout %d, delay %d us, max %d us, read %x, check %x\n",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

289

smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

296

smu_print("SMU Frequency set = %d KHz hard_min_done %d\n", response, hard_min_done);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

298

smu_print("SMU Frequency set = %d KHz\n", response);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

305

smu_print("PMFW to wait for DMCUB ack for MCLK : %d\n", enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

206

smu_print("requested_dispclk_khz = %d, actual_dispclk_set_mhz: %d\n", requested_dispclk_khz, actual_dispclk_set_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

239

smu_print("requested_dcfclk_khz = %d, actual_dcfclk_set_mhz: %d\n", requested_dcfclk_khz, actual_dcfclk_set_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

256

smu_print("requested_min_ds_dcfclk_khz = %d, actual_min_ds_dcfclk_mhz: %d\n", requested_min_ds_dcfclk_khz, actual_min_ds_dcfclk_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

273

smu_print("requested_dpp_khz = %d, actual_dppclk_set_mhz: %d\n", requested_dpp_khz, actual_dppclk_set_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

291

smu_print("%s: VBIOSSMC_MSG_SetDisplayIdleOptimizations idle_info = %x\n", __func__, idle_info);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

310

smu_print("%s smu_enable_phy_refclk_pwrdwn = %d\n", __func__, enable ? 1 : 0);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

322

smu_print("%s: SMC_MSG_UpdatePmeRestore\n", __func__);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

373

smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW, param = 0x%x\n", __func__, param);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

379

smu_print("%s: SMC_MSG_AllowZstatesEntry msg_id = DISALLOW, param = 0x%x\n", __func__, param);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

386

smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW_Z10_ONLY, param = 0x%x\n", __func__, param);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

392

smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW_Z8_Z10_ONLY, param = 0x%x\n", __func__, param);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

398

smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW_Z8_ONLY, param = 0x%x\n", __func__, param);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

412

smu_print("%s: msg_id = %d, param = 0x%x, return = 0x%x\n", __func__, msg_id, param, retv);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

426

smu_print("%s: SMU DPREF clk = %d mhz\n", __func__, dprefclk);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

441

smu_print("%s: get_dtbclk = %dmhz\n", __func__, dtbclk);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

454

smu_print("%s: smu_set_dtbclk = %d\n", __func__, enable ? 1 : 0);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

466

smu_print("%s: smu_enable_48mhz_tmdp_refclk_pwrdwn = %d\n", __func__, enable ? 1 : 0);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

480

smu_print("%s: smu_exit_low_power_state return = %d\n", __func__, retv);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

148

smu_print("SMU Get SMU version\n");

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

153

smu_print("SMU version: %d\n", *version);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

166

smu_print("SMU Check driver if version\n");

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

171

smu_print("SMU driver if version: %d\n", response);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

185

smu_print("SMU Check msg header version\n");

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

190

smu_print("SMU msg header version: %d\n", response);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

201

smu_print("FCLK P-state support value is : %d\n", support);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

209

smu_print("UCLK P-state support value is : %d\n", support);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

220

smu_print("Numways for SubVP : %d\n", num_ways);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

225

smu_print("SMU Set DRAM addr high: %d\n", addr_high);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

233

smu_print("SMU Set DRAM addr low: %d\n", addr_low);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

241

smu_print("SMU Transfer WM table DRAM 2 SMU\n");

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

249

smu_print("SMU Set PME workaround\n");

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

265

smu_print("SMU Get hard min status: no_timeout %d delay %d us clk bits %x\n",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

289

smu_print("SMU Wait hard min status for %d us\n", total_delay_us);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

309

smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

316

smu_print("SMU Frequency set = %d KHz hard_min_done %d\n", response, hard_min_done);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

323

smu_print("SMU to wait for DMCUB ack for MCLK : %d\n", enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

330

smu_print("SMU Set indicate drr status = %d\n", mod_drr_for_pstate);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

346

smu_print("SMU Set idle hardmin by freq: uclk_freq_mhz = %d MHz, fclk_freq_mhz = %d MHz\n", uclk_freq_mhz, fclk_freq_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

353

smu_print("SMU hard_min_done %d\n", success);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

368

smu_print("SMU Set active hardmin by freq: uclk_freq_mhz = %d MHz, fclk_freq_mhz = %d MHz\n", uclk_freq_mhz, fclk_freq_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

375

smu_print("SMU hard_min_done %d\n", success);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

390

smu_print("SMU Set active hardmin by freq: uclk_freq_mhz = %d MHz, fclk_freq_mhz = %d MHz\n", uclk_freq_mhz, fclk_freq_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

400

smu_print("SMU Set min deep sleep dcef clk: freq_mhz = %d MHz\n", freq_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

408

smu_print("SMU Set num of displays: num_displays = %d\n", num_displays);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

420

smu_print("SMU Get Num UMC Channels: num_umc_channels = %d\n", response);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

446

smu_print("SMU Get dpm freq by index: clk = %d, dpm_level = %d\n", clk, dpm_level);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

451

smu_print("SMU dpm freq: %d MHz\n", response);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

464

smu_print("SMU Get DC mode max DPM freq: clk = %d\n", clk);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

469

smu_print("SMU DC mode max DMP freq: %d MHz\n", response);