drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

658

struct smu_dpm_clks *smu_dpm_clks)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

660

struct vg_dpm_clocks *table = smu_dpm_clks->dpm_clks;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

665

if (!table || smu_dpm_clks->mc_address.quad_part == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

671

smu_dpm_clks->mc_address.high_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

673

smu_dpm_clks->mc_address.low_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

683

struct smu_dpm_clks smu_dpm_clks = { 0 };

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

711

smu_dpm_clks.dpm_clks = (struct vg_dpm_clocks *)dm_helpers_allocate_gpu_mem(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

715

&smu_dpm_clks.mc_address.quad_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

717

if (smu_dpm_clks.dpm_clks == NULL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

718

smu_dpm_clks.dpm_clks = &dummy_clocks;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

719

smu_dpm_clks.mc_address.quad_part = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

722

ASSERT(smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

749

vg_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

754

smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

757

if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

759

smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

501

struct dcn31_smu_dpm_clks *smu_dpm_clks)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

503

DpmClocks_t *table = smu_dpm_clks->dpm_clks;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

508

if (!table || smu_dpm_clks->mc_address.quad_part == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

514

smu_dpm_clks->mc_address.high_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

516

smu_dpm_clks->mc_address.low_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

679

struct dcn31_smu_dpm_clks smu_dpm_clks = { 0 };

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

707

smu_dpm_clks.dpm_clks = (DpmClocks_t *)dm_helpers_allocate_gpu_mem(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

711

&smu_dpm_clks.mc_address.quad_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

713

if (smu_dpm_clks.dpm_clks == NULL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

714

smu_dpm_clks.dpm_clks = &dummy_clocks;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

715

smu_dpm_clks.mc_address.quad_part = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

718

ASSERT(smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

748

dcn31_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

757

smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

758

smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

759

smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

760

smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

761

smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

762

smu_dpm_clks.dpm_clks->MinGfxClk,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

763

smu_dpm_clks.dpm_clks->MaxGfxClk);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

764

for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

767

smu_dpm_clks.dpm_clks->DcfClocks[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

769

for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

771

i, smu_dpm_clks.dpm_clks->DispClocks[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

773

for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

775

i, smu_dpm_clks.dpm_clks->SocClocks[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

779

i, smu_dpm_clks.dpm_clks->SocVoltage[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

785

i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

786

i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

787

i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

793

smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

797

if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

799

smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

572

struct dcn314_smu_dpm_clks *smu_dpm_clks)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

574

DpmClocks314_t *table = smu_dpm_clks->dpm_clks;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

579

if (!table || smu_dpm_clks->mc_address.quad_part == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

585

smu_dpm_clks->mc_address.high_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

587

smu_dpm_clks->mc_address.low_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

796

struct dcn314_smu_dpm_clks smu_dpm_clks = { 0 };

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

824

smu_dpm_clks.dpm_clks = (DpmClocks314_t *)dm_helpers_allocate_gpu_mem(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

828

&smu_dpm_clks.mc_address.quad_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

830

if (smu_dpm_clks.dpm_clks == NULL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

831

smu_dpm_clks.dpm_clks = &dummy_clocks;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

832

smu_dpm_clks.mc_address.quad_part = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

835

ASSERT(smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

865

dcn314_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

873

smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

874

smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

875

smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

876

smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

877

smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

878

smu_dpm_clks.dpm_clks->MinGfxClk,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

879

smu_dpm_clks.dpm_clks->MaxGfxClk);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

880

for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

883

smu_dpm_clks.dpm_clks->DcfClocks[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

885

for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

887

i, smu_dpm_clks.dpm_clks->DispClocks[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

889

for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

891

i, smu_dpm_clks.dpm_clks->SocClocks[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

895

i, smu_dpm_clks.dpm_clks->SocVoltage[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

901

i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

902

i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

903

i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

910

smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

914

if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

916

smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

461

struct dcn315_smu_dpm_clks *smu_dpm_clks)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

463

DpmClocks_315_t *table = smu_dpm_clks->dpm_clks;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

468

if (!table || smu_dpm_clks->mc_address.quad_part == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

474

smu_dpm_clks->mc_address.high_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

476

smu_dpm_clks->mc_address.low_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

609

struct dcn315_smu_dpm_clks smu_dpm_clks = { 0 };

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

637

smu_dpm_clks.dpm_clks = (DpmClocks_315_t *)dm_helpers_allocate_gpu_mem(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

641

&smu_dpm_clks.mc_address.quad_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

643

if (smu_dpm_clks.dpm_clks == NULL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

644

smu_dpm_clks.dpm_clks = &dummy_clocks;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

645

smu_dpm_clks.mc_address.quad_part = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

648

ASSERT(smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

675

dcn315_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

683

smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

684

smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

685

smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

686

smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

687

smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

688

smu_dpm_clks.dpm_clks->MinGfxClk,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

689

smu_dpm_clks.dpm_clks->MaxGfxClk);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

690

for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

693

smu_dpm_clks.dpm_clks->DcfClocks[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

695

for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

697

i, smu_dpm_clks.dpm_clks->DispClocks[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

699

for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

701

i, smu_dpm_clks.dpm_clks->SocClocks[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

705

i, smu_dpm_clks.dpm_clks->SocVoltage[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

711

i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

712

i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

713

i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

720

smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

724

if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

726

smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

427

struct dcn316_smu_dpm_clks *smu_dpm_clks)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

429

DpmClocks_316_t *table = smu_dpm_clks->dpm_clks;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

434

if (!table || smu_dpm_clks->mc_address.quad_part == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

440

smu_dpm_clks->mc_address.high_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

442

smu_dpm_clks->mc_address.low_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

584

struct dcn316_smu_dpm_clks smu_dpm_clks = { 0 };

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

612

smu_dpm_clks.dpm_clks = (DpmClocks_316_t *)dm_helpers_allocate_gpu_mem(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

616

&smu_dpm_clks.mc_address.quad_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

618

if (smu_dpm_clks.dpm_clks == NULL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

619

smu_dpm_clks.dpm_clks = &dummy_clocks;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

620

smu_dpm_clks.mc_address.quad_part = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

623

ASSERT(smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

658

dcn316_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

664

smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

668

if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

670

smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1403

struct dcn35_smu_dpm_clks smu_dpm_clks = { 0 };

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1436

smu_dpm_clks.dpm_clks = (DpmClocks_t_dcn35 *)dm_helpers_allocate_gpu_mem(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1440

&smu_dpm_clks.mc_address.quad_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1441

if (smu_dpm_clks.dpm_clks == NULL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1442

smu_dpm_clks.dpm_clks = &dummy_clocks;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1443

smu_dpm_clks.mc_address.quad_part = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1445

ASSERT(smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1489

translate_to_DpmClocks_t_dcn35(&smu_dpm_clks_dcn351, &smu_dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1491

dcn35_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1500

smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1501

smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1502

smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1503

smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1504

smu_dpm_clks.dpm_clks->NumFclkLevelsEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1505

smu_dpm_clks.dpm_clks->NumMemPstatesEnabled,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1506

smu_dpm_clks.dpm_clks->MinGfxClk,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1507

smu_dpm_clks.dpm_clks->MaxGfxClk);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1508

for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1511

smu_dpm_clks.dpm_clks->DcfClocks[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1513

for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1515

i, smu_dpm_clks.dpm_clks->DispClocks[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1517

for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1519

i, smu_dpm_clks.dpm_clks->SocClocks[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1521

for (i = 0; i < smu_dpm_clks.dpm_clks->NumFclkLevelsEnabled; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1523

i, smu_dpm_clks.dpm_clks->FclkClocks_Freq[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1525

i, smu_dpm_clks.dpm_clks->FclkClocks_Voltage[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1527

for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1529

i, smu_dpm_clks.dpm_clks->SocVoltage[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1531

for (i = 0; i < smu_dpm_clks.dpm_clks->NumMemPstatesEnabled; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1535

i, smu_dpm_clks.dpm_clks->MemPstateTable[i].UClk,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1536

i, smu_dpm_clks.dpm_clks->MemPstateTable[i].MemClk,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1537

i, smu_dpm_clks.dpm_clks->MemPstateTable[i].Voltage);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1544

smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1548

if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1550

smu_dpm_clks.dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

943

struct dcn35_smu_dpm_clks *smu_dpm_clks)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

945

DpmClocks_t_dcn35 *table = smu_dpm_clks->dpm_clks;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

950

if (!table || smu_dpm_clks->mc_address.quad_part == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

956

smu_dpm_clks->mc_address.high_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

958

smu_dpm_clks->mc_address.low_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

963

struct dcn351_smu_dpm_clks *smu_dpm_clks)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

965

DpmClocks_t_dcn351 *table = smu_dpm_clks->dpm_clks;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

969

if (!table || smu_dpm_clks->mc_address.quad_part == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

973

smu_dpm_clks->mc_address.high_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

975

smu_dpm_clks->mc_address.low_part);