smsc95xx_write_reg
ret = smsc95xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_);
ret = smsc95xx_write_reg(dev, LED_GPIO_CFG, read_buf);
ret = smsc95xx_write_reg(dev, FLOW, 0);
ret = smsc95xx_write_reg(dev, AFC_CFG, AFC_CFG_DEFAULT);
ret = smsc95xx_write_reg(dev, VLAN1, (u32)ETH_P_8021Q);
ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf);
ret = smsc95xx_write_reg(dev, PM_CTRL, val);
ret = smsc95xx_write_reg(dev, PM_CTRL, val);
ret = smsc95xx_write_reg(dev, PM_CTRL, val);
ret = smsc95xx_write_reg(dev, PM_CTRL, val);
ret = smsc95xx_write_reg(dev, PM_CTRL, val);
ret = smsc95xx_write_reg(dev, PM_CTRL, val);
ret = smsc95xx_write_reg(dev, PM_CTRL, val);
ret = smsc95xx_write_reg(dev, WUCSR, val);
ret = smsc95xx_write_reg(dev, PM_CTRL, val);
ret = smsc95xx_write_reg(dev, WUFF, filter_mask[i]);
ret = smsc95xx_write_reg(dev, WUFF, command[i]);
ret = smsc95xx_write_reg(dev, WUFF, offset[i]);
ret = smsc95xx_write_reg(dev, WUFF, crc[i]);
ret = smsc95xx_write_reg(dev, WUCSR, val);
ret = smsc95xx_write_reg(dev, WUCSR, val);
ret = smsc95xx_write_reg(dev, WUCSR, val);
ret = smsc95xx_write_reg(dev, PM_CTRL, val);
ret = smsc95xx_write_reg(dev, WUCSR, val);
ret = smsc95xx_write_reg(dev, PM_CTRL, val);
ret = smsc95xx_write_reg(dev, MII_ADDR, addr);
ret = smsc95xx_write_reg(dev, MII_DATA, val);
ret = smsc95xx_write_reg(dev, MII_ADDR, addr);
ret = smsc95xx_write_reg(dev, PM_CTRL, val);
ret = smsc95xx_write_reg(dev, E2P_CMD, val);
ret = smsc95xx_write_reg(dev, E2P_CMD, val);
ret = smsc95xx_write_reg(dev, E2P_DATA, val);
ret = smsc95xx_write_reg(dev, E2P_CMD, val);
ret = smsc95xx_write_reg(dev, FLOW, flow);
return smsc95xx_write_reg(dev, AFC_CFG, afc_cfg);
ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
ret = smsc95xx_write_reg(dev, COE_CR, read_buf);
ret = smsc95xx_write_reg(dev, ADDRL, addr_lo);
return smsc95xx_write_reg(dev, ADDRH, addr_hi);
ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
return smsc95xx_write_reg(dev, TX_CFG, TX_CFG_ON_);
return smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
ret = smsc95xx_write_reg(dev, HW_CFG, HW_CFG_LRST_);
ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap);