smi_write
smi_write(IR_Idle_Cnt_Low,
smi_write(MSI_INT_ENA_SET, IR_X_INT);
smi_write(MSI_INT_ENA_CLR, IR_X_INT);
smi_write(MSI_INT_STATUS_CLR, IR_X_INT);
smi_write(MSI_INT_ENA_CLR, ALL_INT);
smi_write(MSI_INT_ENA_CLR,
smi_write(MSI_INT_ENA_SET,
smi_write(MSI_INT_STATUS_CLR,
smi_write(MUX_MODE_CTRL, port_mux);
smi_write(port->DMA_MANAGEMENT, dmaManagement);
smi_write(VIDEO_CTRL_STATUS_A, port_ctrl);
smi_write(MPEG2_CTRL_A, port_ctrl);
smi_write(VIDEO_CTRL_STATUS_B, port_ctrl);
smi_write(MPEG2_CTRL_B, port_ctrl);
smi_write(MSI_INT_ENA_CLR, ALL_INT);
smi_write(MSI_INT_STATUS_CLR, int_stat);
smi_write(sw_ctl, dwCtrl);
smi_write(sw_ctl, dwCtrl);
smi_write(port->DMA_CHAN0_ADDR_LOW, dmaMemPtrLow);
smi_write(port->DMA_CHAN0_ADDR_HI, dmaMemPtrHi);
smi_write(port->DMA_CHAN0_CONTROL, dmaCtlReg);
smi_write(port->DMA_CHAN1_ADDR_LOW, dmaMemPtrLow);
smi_write(port->DMA_CHAN1_ADDR_HI, dmaMemPtrHi);
smi_write(port->DMA_CHAN1_CONTROL, dmaCtlReg);
smi_write(port->DMA_MANAGEMENT, dmaManagement);