set_val
static void sunxi_setbits(void __iomem *reg, u32 set_val)
reg_val |= set_val;
static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val)
reg_val |= set_val;
u8 shift, u8 width, u32 set_val)
regmap_update_bits(membase, reg, mask, set_val << shift);
u32 set_val = val & ~mask;
memcpy((u8 *)fs + offset, &set_val, size);
u32 cfg_reg, u32 set_val,
regmap_write(mdio_dev->subctrl_vbase, cfg_reg, set_val);
u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
if (val == set_val)
if (val != set_val) {
int set_val = 0;
set_val = 1;
dev_dbg(common->dev, "set offload_fwd_mark %d\n", set_val);
priv->offload_fwd_mark = set_val;
int set_val = 0;
set_val = 1;
dev_dbg(cpsw->dev, "set offload_fwd_mark %d\n", set_val);
priv->offload_fwd_mark = set_val;
int set_val = 0;
set_val = 1;
dev_dbg(prueth->dev, "set offload_fwd_mark %d\n", set_val);
emac->offload_fwd_mark = set_val;
int set_val = 0;
set_val = 1;
set_val, prueth->br_members);
WRITE_ONCE(prueth->emac[i]->offload_fwd_mark, set_val);
if (set_val && !PRUETH_IS_SWITCH(prueth)) {
void halbtc_set_bt_reg(void *btc_context, u8 reg_type, u32 offset, u32 set_val)
*((__le16 *)&cmd_buffer1[2]) = cpu_to_le16((u16)set_val);
set_val(v, where, size, val);
set_val(v, where, size, val);
set_val(v, where, size, val);
set_val(v, where, size, val);
set_val(v, where, size, val);
set_val(v, where, size, val);
set_val(v, where, size, val);
set_val(v, where, size, val);
set_val(v, where, size, val);
set_val(v, where, size, val);
set_val(v, where, size, val);
set_val(v, where, size, val);
set_val(e0, where, size, val);
set_val(v, where, size, val);
set_val(v, where, size, val);
set_val(v, where, size, val);
if (bank->debounce.set_val[i]) {
bank->debounce.set_val[i] = true;
pctrl->gpio_bank[id].debounce.set_val[i] = false;
bool set_val[NPCM8XX_DEBOUNCE_MAX];
u8 set_val = 0;
set_val = arg;
val = set_val ? BIT(smt_off) : 0;
set_val = arg;
val = set_val ? mask : 0;
set_val = 0;
set_val = 1;
set_val = 2;
set_val = 3;
set_val = 1;
set_val = 0;
val = set_val ? BIT(input_volt_off) : 0;
set_val = arg;
val = set_val << p_off;
set_val = arg;
val = set_val << n_off;
set_val = arg;
val = set_val << sconfig_desc->dcycle_offset;
val |= set_val << pin->dsel_shift;
unsigned int val, set_val, pude_val;
set_val = 0;
set_val = 1;
val |= set_val << pin->pud_shift;
set_val = DIV_ROUND_CLOSEST(arg, 2) - 1;
static int rt5133_gpio_set(struct gpio_chip *chip, unsigned int offset, int set_val)
val = set_val ? mask : 0;
if (set_val)
set_val);
unsigned int set_val;
res = kstrtouint_from_user(buf, count, 0, &set_val);
if (set_val > 0)
int (*set_val)(struct sock *, int),
ret = set_val(ssk, val);
u64 set_val;
set_val = 0;
set_val = FW_REG_ULIMIT_VAL(reg_info->max_feat_bit);
ret = __vcpu_set_reg(vcpu, reg_info->reg, set_val);
(set_val ? "set" : "clear"), reg_info->reg, errno);
TEST_ASSERT(val == set_val,
(set_val ? "set" : "cleared"), reg_info->reg);
if (set_val) {