ADM8211_CSR_READ
ADM8211_CSR_READ(SPR); /* eeprom_delay */
reg = ADM8211_CSR_READ(SYNCTL);
reg = ADM8211_CSR_READ(PLCPHD) & 0x00FFFFFF; /* keep bits 0-23 */
reg = ADM8211_CSR_READ(PAR);
reg = ADM8211_CSR_READ(CSR_TEST1);
reg = ADM8211_CSR_READ(CMDR);
if (ADM8211_CSR_READ(CSR_TEST0) & ADM8211_CSR_TEST0_EPTYP) {
ADM8211_CSR_READ(SYNRF);
ADM8211_CSR_READ(SYNRF);
reg = ADM8211_CSR_READ(CFPP);
ADM8211_CSR_WRITE(STSR, ADM8211_CSR_READ(STSR));
reg = ADM8211_CSR_READ(MACTEST);
reg = ADM8211_CSR_READ(WEPCTL);
ADM8211_CSR_READ(LPC);
tmp = ADM8211_CSR_READ(PAR);
while ((ADM8211_CSR_READ(PAR) & ADM8211_PAR_SWR) && timeout--)
reg = ADM8211_CSR_READ(CSR_TEST1);
reg = ADM8211_CSR_READ(CSR_TEST1);
reg = ADM8211_CSR_READ(CSR_TEST0);
tsftl = ADM8211_CSR_READ(TSFTL);
tsft = ADM8211_CSR_READ(TSFTH);
reg = ADM8211_CSR_READ(ABDA1);
ADM8211_CSR_READ(NAR);
ADM8211_CSR_READ(NAR);
*(__le32 *)perm_addr = cpu_to_le32(ADM8211_CSR_READ(PAR0));
cpu_to_le16(ADM8211_CSR_READ(PAR1) & 0xFFFF);
ADM8211_CSR_READ(FRCTL);
ADM8211_CSR_READ(FRCTL);
ADM8211_CSR_READ(WEPCTL);
ADM8211_CSR_READ(WESK);
u32 reg = ADM8211_CSR_READ(WEPCTL);
u32 reg = ADM8211_CSR_READ(WEPCTL);
u32 stsr = ADM8211_CSR_READ(STSR);
ADM8211_CSR_READ(SYNRF); \
ADM8211_CSR_READ(SYNRF); \
ADM8211_CSR_READ(SYNRF); \
ADM8211_CSR_READ(SYNRF); \
ADM8211_CSR_READ(SYNRF); \
ADM8211_CSR_READ(SYNRF); \
ADM8211_CSR_READ(SYNRF); \
ADM8211_CSR_READ(SYNRF); \
ADM8211_CSR_READ(SYNRF); \
reg = ADM8211_CSR_READ(BBPCTL);
reg = ADM8211_CSR_READ(BBPCTL);
ADM8211_CSR_WRITE(BBPCTL, ADM8211_CSR_READ(BBPCTL) &
reg = ADM8211_CSR_READ(GPIO);
reg = ADM8211_CSR_READ(PLCPHD);
ADM8211_CSR_READ(SYNRF);
reg = ADM8211_CSR_READ(CAP0);
u32 reg = ADM8211_CSR_READ(SPR);
reg = ADM8211_CSR_READ(BBPCTL);
reg = ADM8211_CSR_READ(MMIRD1);
ADM8211_CSR_READ(SYNRF);
ADM8211_CSR_READ(NAR); \
ADM8211_CSR_READ(NAR); \