arch/powerpc/include/asm/book3s/64/mmu-hash.h

720

struct slice_mask mask_64k;

arch/powerpc/include/asm/book3s/64/mmu-hash.h

722

struct slice_mask mask_4k;

arch/powerpc/include/asm/book3s/64/mmu-hash.h

724

struct slice_mask mask_16m;

arch/powerpc/include/asm/book3s/64/mmu-hash.h

725

struct slice_mask mask_16g;

arch/powerpc/include/asm/book3s/64/mmu.h

169

static inline struct slice_mask *slice_mask_for_size(mm_context_t *ctx, int psize)

arch/powerpc/mm/book3s64/slice.c

117

static void slice_mask_for_free(struct mm_struct *mm, struct slice_mask *ret,

arch/powerpc/mm/book3s64/slice.c

139

const struct slice_mask *available,

arch/powerpc/mm/book3s64/slice.c

188

const struct slice_mask *mask, int psize)

arch/powerpc/mm/book3s64/slice.c

193

struct slice_mask *psize_mask, *old_mask;

arch/powerpc/mm/book3s64/slice.c

264

const struct slice_mask *available,

arch/powerpc/mm/book3s64/slice.c

282

const struct slice_mask *available,

arch/powerpc/mm/book3s64/slice.c

324

const struct slice_mask *available,

arch/powerpc/mm/book3s64/slice.c

34

static void slice_print_mask(const char *label, const struct slice_mask *mask)

arch/powerpc/mm/book3s64/slice.c

381

const struct slice_mask *mask, int psize,

arch/powerpc/mm/book3s64/slice.c

390

static inline void slice_copy_mask(struct slice_mask *dst,

arch/powerpc/mm/book3s64/slice.c

391

const struct slice_mask *src)

arch/powerpc/mm/book3s64/slice.c

399

static inline void slice_or_mask(struct slice_mask *dst,

arch/powerpc/mm/book3s64/slice.c

400

const struct slice_mask *src1,

arch/powerpc/mm/book3s64/slice.c

401

const struct slice_mask *src2)

arch/powerpc/mm/book3s64/slice.c

409

static inline void slice_andnot_mask(struct slice_mask *dst,

arch/powerpc/mm/book3s64/slice.c

410

const struct slice_mask *src1,

arch/powerpc/mm/book3s64/slice.c

411

const struct slice_mask *src2)

arch/powerpc/mm/book3s64/slice.c

429

struct slice_mask good_mask;

arch/powerpc/mm/book3s64/slice.c

430

struct slice_mask potential_mask;

arch/powerpc/mm/book3s64/slice.c

431

const struct slice_mask *maskp;

arch/powerpc/mm/book3s64/slice.c

432

const struct slice_mask *compat_maskp = NULL;

arch/powerpc/mm/book3s64/slice.c

48

static void slice_print_mask(const char *label, const struct slice_mask *mask) {}

arch/powerpc/mm/book3s64/slice.c

61

struct slice_mask *ret)

arch/powerpc/mm/book3s64/slice.c

714

struct slice_mask *mask;

arch/powerpc/mm/book3s64/slice.c

760

struct slice_mask mask;

arch/powerpc/mm/book3s64/slice.c

791

const struct slice_mask *maskp;

arch/powerpc/mm/book3s64/slice.c

800

const struct slice_mask *compat_maskp;

arch/powerpc/mm/book3s64/slice.c

801

struct slice_mask available;

drivers/crypto/intel/qat/qat_common/icp_qat_fw_loader_handle.h

19

unsigned int slice_mask;

drivers/crypto/intel/qat/qat_common/qat_hal.c

801

handle->hal_handle->slice_mask = hw_data->accel_mask;

drivers/gpu/drm/i915/display/intel_display.h

87

for_each_if(DISPLAY_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))

drivers/gpu/drm/i915/display/intel_display_device.c

1129

.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \

drivers/gpu/drm/i915/display/intel_display_device.c

1307

.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \

drivers/gpu/drm/i915/display/intel_display_device.c

663

.dbuf.slice_mask = BIT(DBUF_S1),

drivers/gpu/drm/i915/display/intel_display_device.c

813

.dbuf.slice_mask = BIT(DBUF_S1), \

drivers/gpu/drm/i915/display/intel_display_device.c

872

.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \

drivers/gpu/drm/i915/display/intel_display_device.c

962

.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \

drivers/gpu/drm/i915/display/intel_display_device.h

316

u8 slice_mask;

drivers/gpu/drm/i915/display/intel_display_power.c

1090

u8 slice_mask = DISPLAY_INFO(display)->dbuf.slice_mask;

drivers/gpu/drm/i915/display/intel_display_power.c

1093

drm_WARN(display->drm, req_slices & ~slice_mask,

drivers/gpu/drm/i915/display/intel_display_power.c

1095

req_slices, slice_mask);

drivers/gpu/drm/i915/display/skl_watermark.c

2551

DISPLAY_INFO(display)->dbuf.slice_mask,

drivers/gpu/drm/i915/display/skl_watermark.c

410

hweight8(DISPLAY_INFO(display)->dbuf.slice_mask);

drivers/gpu/drm/i915/display/skl_watermark.c

414

skl_ddb_entry_for_slices(struct intel_display *display, u8 slice_mask,

drivers/gpu/drm/i915/display/skl_watermark.c

419

if (!slice_mask) {

drivers/gpu/drm/i915/display/skl_watermark.c

425

ddb->start = (ffs(slice_mask) - 1) * slice_size;

drivers/gpu/drm/i915/display/skl_watermark.c

426

ddb->end = fls(slice_mask) * slice_size;

drivers/gpu/drm/i915/display/skl_watermark.c

432

static unsigned int mbus_ddb_offset(struct intel_display *display, u8 slice_mask)

drivers/gpu/drm/i915/display/skl_watermark.c

436

if (slice_mask & (BIT(DBUF_S1) | BIT(DBUF_S2)))

drivers/gpu/drm/i915/display/skl_watermark.c

437

slice_mask = BIT(DBUF_S1);

drivers/gpu/drm/i915/display/skl_watermark.c

438

else if (slice_mask & (BIT(DBUF_S3) | BIT(DBUF_S4)))

drivers/gpu/drm/i915/display/skl_watermark.c

439

slice_mask = BIT(DBUF_S3);

drivers/gpu/drm/i915/display/skl_watermark.c

441

skl_ddb_entry_for_slices(display, slice_mask, &ddb);

drivers/gpu/drm/i915/display/skl_watermark.c

451

u8 slice_mask = 0;

drivers/gpu/drm/i915/display/skl_watermark.c

464

slice_mask |= BIT(start_slice);

drivers/gpu/drm/i915/display/skl_watermark.c

468

return slice_mask;

drivers/gpu/drm/i915/gem/i915_gem_context.c

1000

if (sseu.slice_mask && !WARN_ON(ce->engine->class != RENDER_CLASS))

drivers/gpu/drm/i915/gem/i915_gem_context.c

1915

if (!user->slice_mask || !user->subslice_mask ||

drivers/gpu/drm/i915/gem/i915_gem_context.c

1927

if (overflows_type(user->slice_mask, context->slice_mask) ||

drivers/gpu/drm/i915/gem/i915_gem_context.c

1936

if (user->slice_mask & ~device->slice_mask)

drivers/gpu/drm/i915/gem/i915_gem_context.c

1945

context->slice_mask = user->slice_mask;

drivers/gpu/drm/i915/gem/i915_gem_context.c

1952

unsigned int hw_s = hweight8(device->slice_mask);

drivers/gpu/drm/i915/gem/i915_gem_context.c

1954

unsigned int req_s = hweight8(context->slice_mask);

drivers/gpu/drm/i915/gem/i915_gem_context.c

2509

user_sseu.slice_mask = ce->sseu.slice_mask;

drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c

1170

unsigned int slices = hweight32(ce->engine->sseu.slice_mask);

drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c

1227

hweight32(sseu.slice_mask), spin);

drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c

1272

if (hweight32(engine->sseu.slice_mask) < 2)

drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c

1283

pg_sseu.slice_mask = 1;

drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c

1289

hweight32(engine->sseu.slice_mask),

drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c

1290

hweight32(pg_sseu.slice_mask));

drivers/gpu/drm/i915/gt/intel_sseu.c

158

sseu->slice_mask |= BIT(0);

drivers/gpu/drm/i915/gt/intel_sseu.c

174

sseu->slice_mask |= BIT(0);

drivers/gpu/drm/i915/gt/intel_sseu.c

336

sseu->slice_mask = BIT(0);

drivers/gpu/drm/i915/gt/intel_sseu.c

387

sseu->slice_mask = REG_FIELD_GET(GEN8_F2_S_ENA_MASK, fuse2);

drivers/gpu/drm/i915/gt/intel_sseu.c

405

if (!(sseu->slice_mask & BIT(s)))

drivers/gpu/drm/i915/gt/intel_sseu.c

460

!IS_GEN9_LP(i915) && hweight8(sseu->slice_mask) > 1;

drivers/gpu/drm/i915/gt/intel_sseu.c

491

sseu->slice_mask = REG_FIELD_GET(GEN8_F2_S_ENA_MASK, fuse2);

drivers/gpu/drm/i915/gt/intel_sseu.c

517

if (!(sseu->slice_mask & BIT(s)))

drivers/gpu/drm/i915/gt/intel_sseu.c

562

sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1;

drivers/gpu/drm/i915/gt/intel_sseu.c

584

sseu->slice_mask = BIT(0);

drivers/gpu/drm/i915/gt/intel_sseu.c

588

sseu->slice_mask = BIT(0);

drivers/gpu/drm/i915/gt/intel_sseu.c

592

sseu->slice_mask = BIT(0) | BIT(1);

drivers/gpu/drm/i915/gt/intel_sseu.c

613

intel_sseu_set_info(sseu, hweight8(sseu->slice_mask),

drivers/gpu/drm/i915/gt/intel_sseu.c

677

slices = hweight8(req_sseu->slice_mask);

drivers/gpu/drm/i915/gt/intel_sseu.c

784

hweight8(sseu->slice_mask), sseu->slice_mask);

drivers/gpu/drm/i915/gt/intel_sseu.c

867

for (s = 0; s < fls(sseu->slice_mask); s++)

drivers/gpu/drm/i915/gt/intel_sseu.c

877

unsigned long slice_mask = 0;

drivers/gpu/drm/i915/gt/intel_sseu.c

881

8 * sizeof(slice_mask));

drivers/gpu/drm/i915/gt/intel_sseu.c

886

slice_mask |= BIT(i);

drivers/gpu/drm/i915/gt/intel_sseu.c

892

return slice_mask;

drivers/gpu/drm/i915/gt/intel_sseu.h

102

u8 slice_mask;

drivers/gpu/drm/i915/gt/intel_sseu.h

112

.slice_mask = sseu->slice_mask,

drivers/gpu/drm/i915/gt/intel_sseu.h

69

u8 slice_mask;

drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c

142

sseu->slice_mask |= BIT(s);

drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c

177

sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;

drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c

179

if (sseu->slice_mask) {

drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c

181

for (s = 0; s < fls(sseu->slice_mask); s++)

drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c

187

for (s = 0; s < fls(sseu->slice_mask); s++) {

drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c

203

sseu->slice_mask);

drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c

205

hweight8(sseu->slice_mask));

drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c

38

sseu->slice_mask = BIT(0);

drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c

89

sseu->slice_mask |= BIT(s);

drivers/gpu/drm/i915/gt/intel_workarounds.c

1159

slice = ffs(sseu->slice_mask) - 1;

drivers/gpu/drm/i915/gt/intel_workarounds.c

1308

GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);

drivers/gpu/drm/i915/gt/intel_workarounds.c

1336

unsigned long slice, subslice = 0, slice_mask = 0;

drivers/gpu/drm/i915/gt/intel_workarounds.c

1367

slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask,

drivers/gpu/drm/i915/gt/intel_workarounds.c

1381

if (slice_mask & lncf_mask) {

drivers/gpu/drm/i915/gt/intel_workarounds.c

1382

slice_mask &= lncf_mask;

drivers/gpu/drm/i915/gt/intel_workarounds.c

1387

if (slice_mask & gt->info.mslice_mask) {

drivers/gpu/drm/i915/gt/intel_workarounds.c

1388

slice_mask &= gt->info.mslice_mask;

drivers/gpu/drm/i915/gt/intel_workarounds.c

1392

slice = __ffs(slice_mask);

drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c

900

hweight8(gt->info.sseu.slice_mask));

drivers/gpu/drm/i915/i915_getparam.c

175

value = sseu->slice_mask;

drivers/gpu/drm/i915/i915_perf.c

3172

out_sseu->slice_mask = 0x1;

drivers/gpu/drm/i915/i915_query.c

44

BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));

drivers/gpu/drm/i915/i915_query.c

49

slice_length = sizeof(sseu->slice_mask);

drivers/gpu/drm/i915/i915_query.c

75

&sseu->slice_mask, slice_length))

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

114

u32 slice_mask;

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

102

a6xx_gpu->slice_mask = slice_mask;

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

106

slice_mask &= a6xx_llc_read(a6xx_gpu,

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

109

a6xx_gpu->slice_mask = slice_mask;

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

112

adreno_gpu->chip_id |= FIELD_PREP(GENMASK(7, 4), hweight32(slice_mask));

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

117

return ffs(a6xx_gpu->slice_mask) - 1;

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

90

u32 slice_mask;

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

95

if (a6xx_gpu->slice_mask)

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

98

slice_mask = GENMASK(info->max_slices - 1, 0);

include/uapi/drm/i915_drm.h

2218

__u64 slice_mask;

tools/include/uapi/drm/i915_drm.h

2218

__u64 slice_mask;