slic_write
slic_write(sdev, SLIC_REG_WPHY, val);
slic_write(sdev, SLIC_REG_WPHY, val);
slic_write(sdev, SLIC_REG_WRADDRAL, val);
slic_write(sdev, SLIC_REG_WRADDRBL, val);
slic_write(sdev, SLIC_REG_RBAR, lower_32_bits(paddr) |
slic_write(sdev, SLIC_REG_WRADDRAH, val);
slic_write(sdev, SLIC_REG_WRADDRBH, val);
slic_write(sdev, SLIC_REG_RCV_WCS, SLIC_RCVWCS_BEGIN);
slic_write(sdev, SLIC_REG_RCV_WCS, addr);
slic_write(sdev, SLIC_REG_RCV_WCS, instr);
slic_write(sdev, SLIC_REG_RCV_WCS, instr);
slic_write(sdev, SLIC_REG_RCV_WCS, SLIC_RCVWCS_FINISH);
slic_write(sdev, SLIC_REG_WCS, base + addr);
slic_write(sdev, SLIC_REG_WCS, instr);
slic_write(sdev, SLIC_REG_WCS, instr);
slic_write(sdev, SLIC_REG_WCS,
slic_write(sdev, SLIC_REG_WCS, instr);
slic_write(sdev, SLIC_REG_WCS, instr);
slic_write(sdev, SLIC_REG_WCS, SLIC_WCS_START);
slic_write(sdev, SLIC_REG_ICR, SLIC_ICR_INT_OFF);
slic_write(sdev, SLIC_REG_ISP, lower_32_bits(sm->isr_paddr));
slic_write(sdev, SLIC_REG_INTAGG, 0);
slic_write(sdev, SLIC_REG_ISR, 0);
slic_write(sdev, SLIC_REG_ICR, SLIC_ICR_INT_ON);
slic_write(sdev, SLIC_REG_ICR, SLIC_ICR_INT_OFF);
slic_write(sdev, SLIC_REG_ISR, 0);
slic_write(sdev, SLIC_REG_WXCFG, val);
slic_write(sdev, SLIC_REG_WRCFG, val);
slic_write(sdev, SLIC_REG_WPHY, val);
slic_write(sdev, SLIC_REG_QUIESCE, 0);
slic_write(sdev, SLIC_REG_CBAR, cbar_val);
slic_write(sdev, reg, lower_32_bits(upr->paddr));
slic_write(sdev, SLIC_REG_ICR, SLIC_ICR_INT_OFF);
slic_write(sdev, SLIC_REG_ISP, lower_32_bits(sm->isr_paddr));
slic_write(sdev, SLIC_REG_ISP, 0);
slic_write(sdev, SLIC_REG_ISR, 0);
slic_write(sdev, SLIC_REG_WRCFG, val);
slic_write(sdev, SLIC_REG_WXCFG, val);
slic_write(sdev, SLIC_REG_WMCFG, val);
slic_write(sdev, SLIC_REG_MCASTLOW, lower_32_bits(mcmask));
slic_write(sdev, SLIC_REG_MCASTHIGH, upper_32_bits(mcmask));
slic_write(sdev, SLIC_REG_HBAR, lower_32_bits(paddr) + offset);
slic_write(sdev, SLIC_REG_ISR, 0);
slic_write(sdev, SLIC_REG_ICR, SLIC_ICR_INT_MASK);
slic_write(sdev, SLIC_REG_ISR, 0);
slic_write(sdev, SLIC_REG_RESET, SLIC_RESET_MAGIC);
slic_write(sdev, SLIC_REG_RBAR, lower_32_bits(paddr) |
slic_write(sdev, SLIC_REG_WPHY, val);
slic_write(sdev, SLIC_REG_WPHY, val);
slic_write(sdev, SLIC_REG_WPHY, val);
slic_write(sdev, SLIC_REG_WPHY, val);
slic_write(sdev, SLIC_REG_WPHY, val);
slic_write(spi, DS26522_RIOCR_ADDR,
slic_write(spi, DS26522_TCR1_ADDR, DS26522_TCR1_TB8ZS);
slic_write(spi, DS26522_TIOCR_ADDR,
slic_write(spi, DS26522_E1TAF_ADDR, DS26522_E1TAF_DEFAULT);
slic_write(spi, DS26522_E1TNAF_ADDR, DS26522_E1TNAF_DEFAULT);
slic_write(spi, DS26522_RMMR_ADDR, slic_read(spi, DS26522_RMMR_ADDR) |
slic_write(spi, DS26522_TMMR_ADDR, slic_read(spi, DS26522_TMMR_ADDR) |
slic_write(spi, DS26522_LTRCR_ADDR, DS26522_LTRCR_E1);
slic_write(spi, DS26522_LTITSR_ADDR,
slic_write(spi, DS26522_LRISMR_ADDR,
slic_write(spi, DS26522_LMCR_ADDR, DS26522_LMCR_TE);
slic_write(spi, DS26522_GTCCR_ADDR, DS26522_GTCCR_BPREFSEL_REFCLKIN |
slic_write(spi, DS26522_GTCR2_ADDR, DS26522_GTCR2_TSSYNCOUT);
slic_write(spi, DS26522_GFCR_ADDR, DS26522_GFCR_BPCLK_2048KHZ);
slic_write(spi, DS26522_GTCR1_ADDR, DS26522_GTCR1);
slic_write(spi, DS26522_GLSRR_ADDR, DS26522_GLSRR_RESET);
slic_write(spi, DS26522_GFSRR_ADDR, DS26522_GFSRR_RESET);
slic_write(spi, DS26522_GLSRR_ADDR, DS26522_GLSRR_NORMAL);
slic_write(spi, DS26522_GFSRR_ADDR, DS26522_GFSRR_NORMAL);
slic_write(spi, DS26522_RMMR_ADDR, DS26522_RMMR_SFTRST);
slic_write(spi, DS26522_TMMR_ADDR, DS26522_TMMR_SFTRST);
slic_write(spi, addr, 0);
slic_write(spi, addr, 0);
slic_write(spi, addr, 0);
slic_write(spi, addr, 0);
slic_write(spi, DS26522_GTCR1_ADDR, 0x00);
slic_write(spi, DS26522_RMMR_ADDR, DS26522_RMMR_E1);
slic_write(spi, DS26522_TMMR_ADDR, DS26522_TMMR_E1);
slic_write(spi, DS26522_RMMR_ADDR,
slic_write(spi, DS26522_TMMR_ADDR,
slic_write(spi, DS26522_RCR1_ADDR,