set_bits
u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits)
acr |= set_bits;
extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits);
set_bits(BIT_MASK(nr), addr + BIT_WORD(nr));
DEFINE_BITOP(set_bits, or, "")
set_bits(_TIF_RESTOREALL, ¤t_thread_info()->flags);
set_bits(tsr_bits, &vcpu->arch.tsr);
set_bits(op, &sw_desc->flags);
set_bits(op, &sw_desc->flags);
set_bits(op, &desc->flags);
int clear_bits, int set_bits)
int clear_bits, int set_bits);
int clear_bits, int set_bits)
return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
int clear_bits, int set_bits)
return update_phy_reg(ohci, addr, clear_bits, set_bits);
u64 set_bits, clear_bits;
set_bits = bits[bank] & mask[bank];
writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET);
u32 set_bits, wait_bits;
set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
intel_de_rmw(display, reg, 0, set_bits);
u32 set_bits = 0;
set_bits |= (1 << bit);
vgpu_vreg(vgpu, isr) |= set_bits;
vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr));
dpu_reg_set(struct dpu_context *ctx, u32 offset, u32 set_bits)
writel(bits | set_bits, ctx->base + offset);
KUNIT_EXPECT_EQ(test, sr_entry->set_bits, param->expected_set_bits);
val |= entry->set_bits;
*cs++ = entry->set_bits;
entry->reg.addr, entry->clr_bits, entry->set_bits,
pentry->set_bits |= e->set_bits;
idx, e->clr_bits, e->set_bits,
val |= entry->set_bits;
reg, entry->clr_bits, entry->set_bits,
u32 mask = entry->clr_bits | entry->set_bits;
if ((val & mask) != entry->set_bits)
offset, mask, entry->set_bits, val & mask);
u32 mask = entry->clr_bits | entry->set_bits;
else if ((val & mask) != entry->set_bits)
offset, mask, entry->set_bits, val & mask);
if (e1->clr_bits & e2->clr_bits || e1->set_bits & e2->set_bits ||
e1->clr_bits & e2->set_bits || e1->set_bits & e2->clr_bits)
u32 set_bits;
.set_bits = entry->reg.addr | entry->set_bits,
entry->set_bits &= ~RING_FORCE_TO_NONPRIV_DENY;
entry->set_bits |= RING_FORCE_TO_NONPRIV_DENY;
u32 val = entry->set_bits;
.set_bits = action->set_bits,
.clr_bits = ~0u, .set_bits = (val_), \
.clr_bits = val_, .set_bits = val_, \
.clr_bits = val_, .set_bits = 0, \
.clr_bits = mask_bits_, .set_bits = val_, \
.clr_bits = (mask_bits_), .set_bits = (val_), \
.set_bits = val_, \
u32 set_bits;
set_bits(type, suffix, value, reg, 0x00ff, 0)
set_bits(type, suffix, value, reg, 0xff00, 8)
set_bits(BOOL, fan_auto1, fan_auto1, GL518_REG_MISC, 0x08, 3);
set_bits(BOOL, beep_enable, beep_enable, GL518_REG_CONF, 0x04, 2);
static inline void vfe_reg_set(struct vfe_device *vfe, u32 reg, u32 set_bits)
writel_relaxed(bits | set_bits, vfe->base + reg);
static inline void vfe_reg_set(struct vfe_device *vfe, u32 reg, u32 set_bits)
writel_relaxed(bits | set_bits, vfe->base + reg);
static inline void vfe_reg_set(struct vfe_device *vfe, u32 reg, u32 set_bits)
writel_relaxed(bits | set_bits, vfe->base + reg);
static inline void vfe_reg_set(struct vfe_device *vfe, u32 reg, u32 set_bits)
writel_relaxed(bits | set_bits, vfe->base + reg);
u32 reg, u32 set_bits)
isp_reg_writel(isp, v | set_bits, mmio_range, reg);
u32 reg, u32 clr_bits, u32 set_bits)
isp_reg_writel(isp, (v & ~clr_bits) | set_bits, mmio_range, reg);
val = set_bits(val, ctrl->val, bit, mask);
p = set_bits(p, stereo, 1, 1 << 1);
p = set_bits(p, rds, 2, 1 << 2);
unsigned short set_bits;
rv->set_bits);
rv->set_bits);
u8 set_bits, u8 clear_bits)
rtlpci->reg_bcn_ctrl_val |= set_bits;
u8 set_bits, u8 clear_bits)
rtlpci->reg_bcn_ctrl_val |= set_bits;
u8 set_bits, u8 clear_bits)
rtlusb->reg_bcn_ctrl_val |= set_bits;
u8 set_bits, u8 clear_bits)
rtlpci->reg_bcn_ctrl_val |= set_bits;
u8 set_bits, u8 clear_bits)
rtlusb->reg_bcn_ctrl_val |= set_bits;
u8 set_bits, u8 clear_bits)
rtlpci->reg_bcn_ctrl_val |= set_bits;
u8 set_bits, u8 clear_bits)
rtlpci->reg_bcn_ctrl_val |= set_bits;
u8 set_bits, u8 clear_bits)
rtlpci->reg_bcn_ctrl_val |= set_bits;
u8 set_bits, u8 clear_bits)
rtlpci->reg_bcn_ctrl_val |= set_bits;
u64 valid_mask, u64 set_bits)
if (set_bits & ~(u64)valid_mask)
data = idt_nt_read(ndev, reg) | (u32)set_bits;
unsigned char set_bits, clear_bits;
set_bits = clear_bits = 0;
set_bits |= RTS;
set_bits |= DTR;
up->curregs[R5] |= set_bits;
unsigned char set_bits, clear_bits, new_reg;
set_bits = clear_bits = 0;
set_bits |= SND_BRK;
new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
unsigned char set_bits, clear_bits;
set_bits = clear_bits = 0;
set_bits |= RTS;
set_bits |= DTR;
uap->curregs[R5] |= set_bits;
set_bits, clear_bits, uap->curregs[R5]);
unsigned char set_bits, clear_bits, new_reg;
set_bits = clear_bits = 0;
set_bits |= SND_BRK;
new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
u32 clr_bits, u32 set_bits)
tmp |= set_bits;
unsigned char set_bits, clear_bits;
set_bits = clear_bits = 0;
set_bits |= RTS;
set_bits |= DTR;
up->curregs[R5] |= set_bits;
unsigned char set_bits, clear_bits, new_reg;
set_bits = clear_bits = 0;
set_bits |= SND_BRK;
new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
u8 set_bits)
return fusb302_i2c_mask_write(chip, address, 0x00, set_bits);
bool set_bits)
if (set_bits)
bool set_bits;
wreq->set_bits);
wreq->set_bits = cond;
const unsigned long set_bits = BIT(BH_Uptodate);
set_mask_bits(&bh->b_state, clear_bits, set_bits);
u64 start, u64 len, unsigned set_bits),
TP_ARGS(tree, start, len, set_bits),
__field( unsigned, set_bits)
__entry->set_bits = set_bits;
__print_flags(__entry->set_bits, "|", EXTENT_FLAGS))
u64 start, u64 len, unsigned set_bits, unsigned clear_bits),
TP_ARGS(tree, start, len, set_bits, clear_bits),
__field( unsigned, set_bits)
__entry->set_bits = set_bits;
__print_flags(__entry->set_bits , "|", EXTENT_FLAGS),
long old, set_bits = BIT(MPTCP_DELEGATE_SCHEDULED) | BIT(action);
old = set_mask_bits(&subflow->delegated_status, 0, set_bits);
assert(old + (inner_iterations * set_bits) == accumulator);
inner_iterations, set_bits, num_bits);
unsigned int set_bits, skip;
for (set_bits = 1; set_bits <= num_bits; set_bits <<= 1) {
skip = num_bits / set_bits;
assert(old + (inner_iterations * set_bits) == accumulator);