sky2_write32
sky2_write32(hw, RB_ADDR(q, RB_START), start);
sky2_write32(hw, RB_ADDR(q, RB_END), end);
sky2_write32(hw, RB_ADDR(q, RB_WP), start);
sky2_write32(hw, RB_ADDR(q, RB_RP), start);
sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
sky2_write32(sky2->hw,
sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
sky2_write32(hw, B0_IMSK, imask);
sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
sky2_write32(hw, B0_IMSK, 0);
sky2_write32(hw, B0_IMSK, imask);
sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
sky2_write32(hw, B0_IMSK, imask);
sky2_write32(hw, B0_IMSK, 0);
sky2_write32(hw, B0_IMSK, imask);
sky2_write32(hw, B2_GP_IO, reg);
sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
sky2_write32(hw, B0_Y2_SP_ICR, 2);
sky2_write32(hw, CPU_WDOG, 0);
sky2_write32(hw, CPU_WDOG, 0);
sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
sky2_write32(hw, B2_I2C_IRQ, 1);
sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
sky2_write32(hw, B0_IMSK, 0);
sky2_write32(hw, B0_IMSK, imask);
sky2_write32(hw, STAT_TX_TIMER_INI,
sky2_write32(hw, STAT_LEV_TIMER_INI,
sky2_write32(hw, STAT_ISR_TIMER_INI,
sky2_write32(sky2->hw,
sky2_write32(hw, B0_Y2_SP_ICR, 2);
sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
sky2_write32(hw, B0_IMSK, 0);
sky2_write32(hw, B0_IMSK, 0);
sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
sky2_write32(hw, Y2_CFG_SPC + reg, val);