sky2_read32
sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
sky2_read32(hw, B0_IMSK);
imask = sky2_read32(hw, B0_IMSK);
sky2_read32(hw, B0_IMSK);
sky2_read32(hw, B0_CTST);
sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
sky2_read32(hw, B0_IMSK);
imask = sky2_read32(hw, B0_IMSK);
sky2_read32(hw, B0_IMSK);
imask = sky2_read32(hw, B0_IMSK);
imask = sky2_read32(hw, B0_IMSK);
sky2_read32(hw, B0_IMSK);
sky2_read32(hw, B0_Y2_SP_LISR);
reg = sky2_read32(hw, B2_GP_IO);
sky2_read32(hw, B2_GP_IO);
if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
u32 status = sky2_read32(hw, B0_HWE_ISRC);
u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
if (sky2_read32(hw, B0_ISRC)) {
u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
sky2_read32(hw, B0_Y2_SP_LISR);
status = sky2_read32(hw, B0_Y2_SP_ISRC2);
if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
sky2_read32(hw, B0_IMSK);
sky2_read32(hw, B0_IMSK);
sky2_read32(hw, B0_Y2_SP_LISR);
u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
sky2_read32(hw, B0_ISRC),
sky2_read32(hw, B0_IMSK),
sky2_read32(hw, B0_Y2_SP_ICR));
sky2_read32(hw, B0_Y2_SP_LISR);
u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
sky2_read32(hw, B0_IMSK);
sky2_read32(hw, B0_IMSK);
sky2_read32(hw, B0_CTST);
return sky2_read32(hw, Y2_CFG_SPC + reg);